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本文设计了一款超低功耗、紧凑型112Gb/s PAM-4收发器，采用5nm FinFET工艺，集成了四分之一速率RX（含3抽头FFE和11抽头DFE均衡）和半速率TX（7b SST DAC驱动器），可补偿高达35dB信道损耗，在112Gb/s下实现BER<1E-6，功耗仅280mW。
Alberto Grassi1, Mehrdad Fahimnia1, Hiroshi Kimura2, Faramarz Bahmani2, Hao Chen2, Alex Wang2, Chen Zhao2, Yuan Fang2, Allen Chen3, Afshin Momtaz1, Namik Kocaman1 Broadcom, Irvine, CA, 2Broadcom, San Jose, CA, 3Broadcom, Fort Collins, CO 1 Abstract This paper presents the design of an ultra-low power, compact 112Gb/s PAM-4 transceiver. Each lane incorporates a quarter rate RX with 3-tap FFE, 11-tap DFE equalization, and a halfrate TX using a 7b SST DAC driver. The transceiver can compensate up to 35dB channel loss at 112Gb/s and achieves BER < 1E-6, dissipating only 280mW including both analog and digital power domains. This work has the best pJ/b/dB FOM as well as the lowest area versus comparable work at this data rate. The increased demand in next-generation data centers and high-performance computing has pushed serial link data rates into 100Gb/s territory and beyond. To cope with channel
Ullas Singh1, Kumar Thasari1, Nitin Nidhi1, Arvindh Iyer1, Saurabh Surana1, Batu Dayanik1, Yuanfang Li1, Mohammadamin Torabi1, Jun Won Jung1,