An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS

📋 论文概要

该论文提出了一种8至28GHz的8相时钟发生器，采用双反馈环形振荡器结构，旨在解决传统PLL分频方法在高频CMOS工艺中难以生成多路低抖动时钟的问题。该设计在28nm CMOS工艺中实现了宽频率范围和低相位误差。

💡 主要创新点

• 提出双反馈环形振荡器架构，通过两个反馈环路优化相位噪声和频率调节范围。
• 在28nm CMOS工艺中实现了8至28GHz的宽频率覆盖，同时保持8相输出的低相位误差。

🏷 关键词

📄 原文摘要

Multi-phase clock generation is among the most critical building blocks in high-speed wireline transceivers. The integrated jitter and phase error of the clocks often dictate the maximum available SNDR at higher frequencies. While the classic method of dividing the differential clocks from a phase locked loop provides excellent phase accuracy with low jitter [1-8], it requires the phase locked loop to generate high frequency clocks at multiples of the output frequency (fout×N). In CMOS processes with fT of around 200~300GHz, the combination of phase locked loop and divider becomes increasingly costly, if not infeasible, in 224Gb/s PAM-4 applications and beyond [9-11]. Quadrature VCOs [12-14] and poly-phase filters [15-17] partly mitigate the issue, but they are sensitive to device mismatches and more importantly, only provide 4 clock phases. The delay locked loop (DLL) consisting of chains of inverters conceptually expands the input clock to any desired

👥 作者与机构

Yechen Tian, Junjie Gu, Weitao He, Shuai Liu, Hao Xu, Na Yan

Fudan University, Shanghai, China