A 1.59pJ/b 112Gb/s PAM-4 and 1.06pJ/b 168Gb/s PAM-8 Resistor-Less 7-Bit SST DAC-Based Transmitter with 8-Tap FFE in 28nm CMOS

📋 论文概要

本文提出一种无电阻的7位SST DAC发射机，集成8抽头前馈均衡器（FFE）和三种类型分段，实现了低寄生电容、紧凑面积和工艺可扩展性。为减少4:1复用器输出的码间干扰抖动，提出双反馈均衡器，在28nm CMOS工艺下支持112Gb/s PAM-4和168Gb/s PAM-8速率，能量效率分别为1.59pJ/b和1.06pJ/b。

💡 主要创新点

• 采用无电阻SST DAC架构，消除大电阻带来的寄生和面积开销，提升高速性能。
• 提出三种类型分段设计（如主段、子段等），优化线性度和功耗。

📄 原文摘要

Abstract A resistor-less 7b SST DAC-based TX with 8-tap FFE and 3 types of segments is presented to achieve low parasitic capacitance, compact area, and scaling friendliness. To reduce intersymbol-interference jitter at the output of a 4:1 multiplexer, a dual-feedback equalizer is proposed. The TX is fabricated in 28nm CMOS with a maximum output swing of 1.1Vppd. The power dissipation is 178mW at 112Gb/s PAM-4 and 168Gb/s PAM-8, and energy efficiency is 1.59pJ/b at PAM-4 and 1.06pJ/b at PAM-8. To support higher serial-link data rates, >100Gb/s transmitters (TXs) [1-8] often employ digital-to-analog converters (DACs) [3-8] for multi-level pulse-amplitude-modulated (PAM) signaling. Current-mode logic (CML) DAC-based TXs [3], [4] are adopted due to their wide bandwidth and good supply noise rejection. Source-series termination (SST) DAC-based TXs [5-8] have been developed due to their low power, large swing, and high linearity

👥 作者与机构

Yao-Hung Tsai, Ming-Han Chuang, Shen-Iuan Liu

National Taiwan University, Taipei, Taiwan