A 112Gb/s PAM-4 SBD Transceiver with Mismatch-Compensated 2×VDD Hybrid and Two-Step Echo Canceller in 28nm CMOS

📋 论文概要

本文提出了一种112Gb/s PAM-4同时双向收发器，采用2×VDD堆叠驱动混合器恢复信号摆幅，并通过联合延迟和压摆率匹配消除动态毛刺，配合两步回波消除器抑制反射，解决了高速SBD传输中的信号完整性问题。在28nm CMOS工艺下实现BER<1E-10和1.73pJ/b能效。

💡 主要创新点

• 采用2×VDD堆叠驱动器的混合器，在低电压下恢复PAM-4信号摆幅
• 联合延迟与压摆率匹配方案，消除高速SBD中的动态毛刺
• 两步回波消除器架构，有效减轻通道反射干扰

🏷 关键词

📄 原文摘要

Abstract A 112Gb/s PAM-4 simultaneous bidirectional (SBD) transceiver in 28nm CMOS is presented. It features a hybrid with a 2×VDD stacked driver to restore signal swing, a joint delay and slew-rate matching scheme to eliminate dynamic glitches, and a two-step echo canceller to mitigate reflections. The transceiver achieves BER < 1E-10 over a 12.7dB loss channel (equivalent to 24.4dB at Nyquist), with 1.73pJ/b energy efficiency and an FoM of 0.14pJ/b/dB. The relentless growth in data traffic demands higher I/O bandwidth density, making simultaneous bidirectional (SBD) signaling attractive for doubling channel throughput and halving equivalent channel loss, positioning it as a promising solution for energy-efficient 112Gb/s communication over medium-reach channels. However, prior SBD transceivers face significant trade-offs. ADC-based solutions [1] can tolerate high channel loss at the cost of prohibitive power consumption due to the digital intensive echo cancellers (ECs).

👥 作者与机构

Huanfa Sun, Shangjie Wei, Yu Su, Chenyao Cao, Yujie Zeng, Yukun He, Zhouchi Duan, Guohe Zhang, Xiaoyan Gui

Xi’an JiaoTong University, Xi’an, China