A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

📋 论文概要

该论文提出了一种基于延迟线的5抽头接收端前馈均衡器，用于200Gb/s的高速有线通信，解决了传统判决反馈均衡器在高速率下的时序限制问题。通过连续时间域实现，避免了多相时钟和采样保持电路，实现了低功耗和高能效。

💡 主要创新点

• 采用连续时间延迟线实现5抽头FFE，无需多相时钟和采样保持电路，简化了设计。
• 通过低频率均衡技术补偿信道损耗，在200Gb/s速率下实现0.43pJ/b的超低功耗。

🏷 关键词

📄 原文摘要

The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time feed-forward equalizers (FFEs) in receivers (RXs) break the timing loop and compensate for electrical and optical impairments [23]. However, it relies on accurate, multiphase, and high-speed sampling clocks. The RX FFEs implemented in the continuous-time domain use active [4-5] or passive [5-6] delay lines, which eliminate clock and interleaved sample-and-hold circuits. In addition, the continuous-time FFE preserves edge information and therefore supports the oversampling clock and data recovery (CDR). This paper presents a 5-tap delay-linebased receiver FFE operating at 200Gb/s and equalizing a 17.2dB-loss channel. The top of Fig. 6.3.1 shows the insertion loss of two on-chip grounded coplanar

👥 作者与机构

Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He

Peking University, Beijing, China