技术领域

Wireline I/O

300 篇相关论文 (2008–2026)

ISSCC 2022 Session 17 Wireline I/O
A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1dB FoM Using a Proportionally Divided Charge Pump
Luya Zhang, Ali Niknejad
Beyond-10GHz frequency synthesizers are ubiquitous building blocks for today’s evergrowing wireless and wireline communication systems. To meet the stringent requirements on data-rate and modulation schemes, the phase no
University of California, Berkeley, CA
ISSCC 2022 Session 17 Wireline I/O
A 56GHz 23mW Fractional-N PLL with 110fs Jitter
Yu Zhao, Onur Memioglu, Behzad Razavi
PAM-4 wireline transmitters operating at 224Gb/s can employ a 56GHz PLL for multiplexing. Such an environment poses several constraints on the design. First, the PLL rms jitter must be no more than a few percent of the s
University of California, Los Angeles, CA
ISSCC 2022 Session 17 Wireline I/O
A 10Gb/s Digital Isolator Using Coupled Split-Ring Resonators with 24kVpk Surge Capability and 100kV/µS Common-Mode Transient Immunity
Jinglin Xu, Ruida Yun, Baoxing Chen
High speed data links play a key role in industrial and medical systems. Galvanic isolation in high-speed links ensures the safety of human operators and instruments. Optoisolators generally achieve high voltage ratings
Analog Devices, Wilmington, MA
ISSCC 2022 Session 17 Wireline I/O
A 2.4pJ/b 100Gb/s 3D-Integrated PAM-4 Optical Transmitter with Segmented SiP MOSCAP Modulators and a 2-Channel 28nm CMOS Driver
Arian Hashemi Talkhooncheh1, Weiwei Zhang2, Minwo Wang1,
David J. Thomson2, Martin Ebert2, Li Ke2, Graham T. Reed2, Azita Emami1 California Institute of Technology, Pasadena, CA University of Southampton, Southampton, United Kingdom 1 2 Data centers continue to require interco
ISSCC 2022 Session 17 Wireline I/O
A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS
Kai Sheng*, Haowei Niu*, Boyang Zhang*, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen
cloud computing, have significantly driven the requirement for high transmission data rates. Polarization diversity coherent detection is an indispensable technique for realizing high-capacity transmission owing to its e
Peking University, Beijing, China *Equally-Credited Authors (ECAs) Eme
ISSCC 2021 Session 8 Wireline I/O
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver
James Bailey1, Hossein Shakiba1, Ehud Nir2, Grigory Marderfeld2,
equalization (e.g. extensive FFE and DFE) of wireline channels. FFE and canonical DFE sizes scale linearly with the number of taps, however the computational complexity of an FFE is much greater than that of a DFE. The c
Peter Krotnev2, Marc-Andre LaCroix2, David Cassan1 Huawei Technologies
ISSCC 2021 Session 8 Wireline I/O
A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET peaking inductor is leveraged to resonate out the parasitic & transistor gate capacitances. A flipped voltage follower buffer is used to isolate the CTLE from the 16 TAHs. The DCgain normalized frequency response at the output of the AFE for various CTLE settings is shown in the Fig. 8.7.3.
P. Mishra1, A. Tan1, B. Helal1, C.R. Ho1, C. Loi1, J. Riani1, J. Sun2, K. Mistry3,
K. Raviprakash1, L. Tse1, M. Davoodi4, M. Takefman3, N. Fan4, P. Prabha4, Q. Liu2, Q. Wang1, R. Nagulapalli5, S. Cyrusian4, S. Jantzi4, S. Scouten3, T. Dusatko6, T. Setya3, V. Giridharan1, V. Gurumoorthy1, V. Karam3, W.
ISSCC 2021 Session 8 Wireline I/O
A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET
R. L. Nguyen1, A. M. Castrillon2, A. Fan1, A. Mellati1, B. T. Reyes2, C. Abidin1,
E. Olsen1, F. Ahmad1, G. Hatcher1, J. Chana3, L. Biolato2, L. Tse4, L. Wang1, L. Wang4, M. Azarmnia1, M. Davoodi1, N. Campos2, N. Fan1, P. Prabha1, Q. Lu1, S. Cyrusian1, S. Dallaire5, S. Ho3, S. Jantzi1, T. Dusatko3, W.
ISSCC 2021 Session 8 Wireline I/O
A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm
Danfeng Xu*1, Yu Kou*1, Paul Lai*,1, Zichuan Cheng1, Tze Yin Cheung2,
Larry Moser1, Yang Zhang1, Xiaolong Liu1, Man Pio Lam1, Haikun Jia2,3, Quan Pan2,4, Wing Hong Szeto2, Chi Fai Tang2, Ka Fai Mak2, Khawar Sarfraz2, Tairan Zhu1, Ming Kwan1, Emily Yim Lee Au1, Cormac Conroy1, Kai Keung Cha
ISSCC 2021 Session 8 Wireline I/O
A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir,
Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Hu
ISSCC 2021 Session 8 Wireline I/O
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS
Marcel A. Kossel1, Vishal Khatri1,4, Matthias Braendli1, Pier Andrea Francese1,
Thomas Morf1, Serdar A. Yonar1, Mridula Prathapan1, Eric J. Lukes2, Raymond A. Richetta2, Carrie Cox3 IBM Research, Rüschlikon, Switzerland IBM Systems and Technology, Rochester, MN 3 IBM Systems and Technology, Durham,
ISSCC 2021 Session 8 Wireline I/O
An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
Minsoo Choi*1, Zhongkai Wang*1, Kyoungtae Lee1, Kwanseo Park1,
for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1-4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by mini
Zhaokai Liu1, Ayan Biswas1, Jaeduk Han2, Elad Alon1 University of Cali
ISSCC 2021 Session 8 Wireline I/O
A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS
Jihwan Kim*1, Sandipan Kundu*1, Ajay Balankutty1, Matthew Beach2,
Bong Chan Kim1, Stephen Kim1, Yutao Liu1, Savyassachi Keshava Murthy1, Priya Wali1, Kai Yu1, Hyung Seok Kim1, Chuan-chang Liu1, Dongseok Shin1, Ariel Cohen3, Yongping Fan1, Frank O’Mahony1 Intel, Hillsboro, OR Foundation
ISSCC 2021 Session 19 Wireline I/O
A MEMS-Based Dynamic Light Focusing System for Single-Cell Precision in Optogenetics
Cem Yalcin1, Nathan Tessema Ersumo1, George Bocchetti1,
Mohammad Meraj Ghanbari1, Nick Antipa1, Sina Faraji Alamouti1, Laura Waller1,2, Daniel Lopez3, Rikky Muller1,2 University of California, Berkeley, CA Chan Zuckerberg Biohub, San Francisco, CA 3 National Institute of Stan
ISSCC 2021 Session 19 Wireline I/O
A Mechanically Flexible Implantable Neural Interface for Computational Imaging and Optogenetic Stimulation over 5.4×5.4mm2 FoV
Sajjad Moazeni*1,2, Eric H. Pollmann*1, Vivek Boominathan3, Filipe A. Cardoso1,
Jacob T. Robinson3, Ashok Veeraraghavan3, Kenneth L. Shepard1 Columbia University, New York, NY University of Washington, Seattle, WA 3 Rice University, Houston, TX 1 2 *Equally-Credited Authors (ECAs) The advent of gene
ISSCC 2021 Session 19 Wireline I/O
Optical Phased-Array FMCW LiDAR with On-Chip Calibration
SungWon Chung, Makoto Nakai, Samer Idres, Yongwei Ni, Hossein Hashemi
Light detection and ranging (lidar) sensors provide high resolution and high accuracy for diverse applications such as autonomous vehicles and three-dimensional imagers. Over the past few years, there has been significan
University of Southern California, Los Angeles, CA
ISSCC 2021 Session 11 Wireline I/O
A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler
Jack W. Holloway1,2, Georgios C. Dogiamis3, Ruonan Han1
Raytheon, Tewksbury, MA 3 Intel, Chandler, AZ 1 The rapid surge of data transmission within computation, storage and communication infrastructures is pushing the speed boundary of traditional copper-based electrical link
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2021 Session 11 Wireline I/O
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS
Ramin Farjadrad1, Kambiz Kaviani1, David Nguyen1, Michael Brown1,
Govert Geelen2, Corné Bastiaansen2, Narendra Rao1, Viswa Popuri1, Greg Shen1, Hamid Khatibi1, Saudas Dey3, Anirban Chatterjee3, David Shen1, Peter Zijlstra2, Harrie Gunnink2, Kebin Zhang1, Venkat Penumuchu1, Oliver Weiss
ISSCC 2021 Session 11 Wireline I/O
A 56Gb/s 50mW NRZ Receiver in 28nm CMOS
Atharav Atharav, Behzad Razavi
The power consumption of wireline transceivers has become increasingly critical as higher data rates and a larger numbers of lanes per chip are sought [1-6]. While attractive for lossy channels, PAM-4 signaling has mostl
University of California, Los Angeles, CA
ISSCC 2021 Session 11 Wireline I/O
A 100Gb/s -8.3dBm-Sensitivity PAM-4 Optical Receiver with
Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS
g. 400G-DR4/FR4) have been developed to address the rapid increase in interconnect BW demand created by data-centric computing [1]. Low-cost 100Gb/s PAM-4 optical transceivers are critical to spur their adoption in high
Hao Li, Jahnavi Sharma, Chun-Ming Hsu, Ganesh Balamurugan, James Jauss
ISSCC 2021 Session 11 Wireline I/O
A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET
Dongseok Shin, Hyung Seok Kim, Chuan-chang Liu, Priya Wali,
100Gb/s+ is rapidly increasing to accommodate the massive data traffic of data centric systems such as Internet-of-things, autonomous driving, cloud computing, etc. In recent publications, a 14GHz LC-PLL was successfully
Savyasaachi Keshava Murthy, Yongping Fan Intel, Hillsboro, OR Interest
ISSCC 2021 Session 11 Wireline I/O
A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links
Zhaowen Wang*, Yudong Zhang*, Yuka Onizuka, Peter R. Kinget
*Equally-Credited Authors (ECAs) The ever-increasing Internet data demand imposes stringent requirements on wireline transceiver speed, jitter, and power. A low-noise, multi-phase clock generator (MPCG) is a crucial buil
Columbia University, New York, NY
ISSCC 2021 Session 11 Wireline I/O
A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications
Kelvin McCollough, Scott D. Huss, James Vandersand, Randall Smith,
Chris Moscone, Qazi Omar Farooq Cadence, Cary, NC With recent AI and big data developments, quickly moving massive amounts of data is paramount to future technologies. Scalable solutions that can sustain higher performan
ISSCC 2021 Session 11 Wireline I/O
A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS
Ravi Shivnaraine1, Marcus van Ierssel1, Kamran Farzan1, Dominic Diclemente1,
George Ng1, Nanyan Wang2, Javid Musayev1, Gairik Dutta1, Masumi Shibata1, Arash Moradi1, Haleh Vahedi1, Manavi Farzad1, Prabhnoor Kainth1, Matt Yu1, Nhat Nguyen2, Jennifer Pham1, Angus McLaren1 Rambus, Toronto, Canada Ra
ISSCC 2021 Session 11 Wireline I/O
A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology
Ramy Yousry*1, Ehung Chen*1, Yu-Ming Ying1, Mohammed Abdullatif1,
Mohammad Elbadry1, Ahmed ElShater1, Tsz-Bin Liu2, Joonyeong Lee1, Dhinessh Ramachandran1, Kaiz Wang2, Chih-Hao Weng2, Mau-Lin Wu2, Tamer Ali1 MediaTek, Irvine, CA MediaTek, Hsinchu, Taiwan 1 2 *Equally-Credited Authors (
ISSCC 2020 Session 6 Wireline I/O
A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS
Pen-Jui Peng1, Sheng-Tsung Lai1, Wei-Hung Wang1, Chiang-Wei Lin1,
satisfy the continuously growing demands for wireline communications [1-5]. Although PAM-4 signaling performs two-fold bandwidth efficiency compared with the NRZ counterpart, the NRZ signal still has the advantage in low
Wei-Chien Huang1, Ted Shih2 Yuan Ze University, Taoyuan, Taiwan 2 Tele
ISSCC 2020 Session 6 Wireline I/O
An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels
Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong
a silicon interposer technology to increase the number of I/O pins. Interfaces with the silicon interposer provide a higher throughput (Gb/s/µm) than other packaging technologies due to the high channel density. To incre
Seoul National University, Seoul, Korea To meet the demand for high me
ISSCC 2020 Session 6 Wireline I/O
Reference-Noise Compensation Scheme for SingleEnded Package-to-Package Links
Xi Chen1, Nikola Nedovic1, Stephen G. Tell2, Sudhir S. Kudva1,
Brian Zimmer1, Thomas H. Greer2, John W. Poulton2, Sanquan Song1, Walker J. Turner2, John M. Wilson2, C. Thomas Gray2 NVIDIA, Santa Clara, CA NVIDIA, Durham, NC 1 2 A recent trend in high-performance systems is distribut
ISSCC 2020 Session 6 Wireline I/O
A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS
Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong
Continuous-rate referenceless clock and data recovery (CDR) circuits are capable of operating over a wide range of data rates in multiple standards. To achieve wide-range operation without an external reference clock, se
Seoul National University, Seoul, Korea
ISSCC 2020 Session 6 Wireline I/O
A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier
Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee,
Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin Samsung El
ISSCC 2020 Session 6 Wireline I/O
A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET
Eric Groen1, Charlie Boecker1, Masum Hossain2, Roxanne Vu1,
Socrates Vamvakos1, Haidang Lin1, Simon Li1, Marcus van Ierssel3, Prashant Choudhary1, Nanyan Wang1, Masumi Shibata3, Mohammad Hossein Taghavi3, Nhat Nguyen1,4, Shaishav Desai1 Rambus, Sunnyvale, CA, 2University of Alber
ISSCC 2020 Session 6 Wireline I/O
A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology
Tamer Ali*1, Ehung Chen*1, Henry Park*1, Ramy Yousry*1,
Yu-Ming Ying1, Mohammed Abdullatif1, Miguel Gandara1, Chun-Cheng Liu2, Po-Shuan Weng2, Huan-Sheng Chen2, Mohammad Elbadry1, Qaiser Nehal1, Kun-Hung Tsai2, Kevin Tan2, Yi-Chieh Huang2, Chung-Hsien Tsai2, Yuyun Chang2, Yua
ISSCC 2020 Session 6 Wireline I/O
A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
Jay Im1, Kevin Zheng1, Adam Chou1, Lei Zhou1, Jae Wook Kim1,
Stanley Chen1, Yipeng Wang2, Hao-Wei Hung2, KeeHian Tan2, Winson Lin1, Arianne Roldan1, Declan Carey3, Ilias Chlis3, Ronan Casey3, Ade Bekele1, Ying Cao1, David Mahashin1, Hong Ahn1, Hongtao Zhang1, Yohan Frans1, Ken Cha
ISSCC 2020 Session 12 Wireline I/O
A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver
Hannes Ramon, Michiel Verplaetse, Michael Vanhoecke, Haolin Li,
DACs with an analog bandwidth (BW) of at least 50GHz to support advanced modulation schemes. CMOS-based DACs are preferred because they support monolithic integration of the DSP and DAC, but the achievable sampling rate
Johan Bauwelinck, Peter Ossieur, Xin Yin, Guy Torfs imec-Ghent Univers
ISSCC 2020 Session 12 Wireline I/O
A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters
Teruo Jyo, Munehiko Nagatani, Josuke Ozaki, Mitsuteru Ishikawa, Hideyuki Nosaka
attention for constructing large-capacity optical core/metro networks and even data center interconnects. Data rates in the next generation of coherent optical transmission systems are expected to exceed 400Gb/s, for whi
NTT, Kanagawa, Japan Digital coherent optical transmission technologie
ISSCC 2020 Session 12 Wireline I/O
A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications
Enrico Sentieri*1, Tino Copani*2, Andrea Paganini1, Matteo Traldi1,
Angelo Palladino1, Antonio Santipo1, Lorenzo Gerosa1, Matteo Repossi1, Gianluca Catrini2, Marta Campo2, Francesco Radice1, Andrea Diodato1, Roberto Pelleriti2, Daniele Baldi1, Laura Tarantini1, Luca Maggi1, Gianluca Rada
ISSCC 2020 Session 12 Wireline I/O
A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control
Hao Li, Ganesh Balamurugan, Meer Sakib, Ranjeet Kumar,
stringent demands on the bandwidth and energy efficiency of data center interconnects, spurring the development of several 400G Ethernet standards [1]. Siliconphotonics-based solutions are of particular interest for low
Hasitha Jayatilleka, Haisheng Rong, James Jaussi, Bryan Casper Intel,
ISSCC 2019 Session 6 Wireline I/O
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS
Danny Yoo1, Mohammad Bagherbeik1, Wahid Rahman1,
circuits (CDR) are ubiquitous in recent receiver designs as a means of lowering power consumption by sampling the data only once per UI. To further reduce power, prior works in pattern-based baud-rate PD
Ali Sheikholeslami1, Hirotaka Tamura2, Takayuki Shibasaki2 University
ISSCC 2019 Session 6 Wireline I/O
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS
Pen-Jui Peng1, Yan-Ting Chen1, Sheng-Tsung Lai1, Chao-Hsuan Chen1,
transmitters to operate at higher speeds. The applications of 400GbE also push the transmitter to be designed at 112Gb/s for a single lane [1-2]. However, the use of advanced processes (<16nm) hardly reduces the costs. T
Hsiang-En Huang1, Ted Shih2 Yuan Ze University, Taoyuan City, Taiwan T
ISSCC 2019 Session 6 Wireline I/O
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
Zeynep Toprak-Deniz, Jonathan E. Proesel, John F. Bulzacchelli,
Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli IBM T. J. Watson Research Center, Yorktown Heights, NY The ever-increasing demand for higher bandwidth continues to fuel the need for faster and
ISSCC 2019 Session 6 Wireline I/O
A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET
C. Loi1, A. Mellati2, A. Tan3, A. Farhoodfar3, A. Tiruvur3, B. Helal3, B. Killips4,
F. Rad3, J. Riani3, J. Pernillo3, J. Sun1, J. Wong3, K. Abdelhalim2, K. Gopalakrishnan3, K. Kim2, L. Tse3, M. Davoodi2, M. Le2, M. Zhang3, M. Talegaonkar2, P. Prabha2, R. Mohanavelu3, S. Chong1, S. Forey4, S. Netto3, S.
ISSCC 2019 Session 6 Wireline I/O
A 180mW 56Gb/s DSP-Based Transceiver for HighDensity IOs in Data Center Switches in 7nm FinFET Technology
Tamer Ali1, Ramy Yousry*1, Henry Park*1, Ehung Chen*1,
Po-Shuan Weng2, Yi-Chieh Huang2, Chun-Cheng Liu2, Chien-Hua Wu2, Shih-Hao Huang2, Chungshi Lin2, Ke-Chung Wu2, Kun-Hung Tsai2, Kai-Wen Tan2, Ahmed ElShater1, Kuang-Ren Chen2, Wei-Hao Tsai2, Huan-Sheng Chen2, Weiyu Leng1,
ISSCC 2019 Session 6 Wireline I/O
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani,
Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta,
ISSCC 2019 Session 6 Wireline I/O
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss
Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho,
Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto Huawei Technologies, Ottawa, ON, Canada With the introduction of PAM
ISSCC 2019 Session 6 Wireline I/O
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
Alessandro Cevrero, Ilter Ozkaya, Pier Andrea Francese, Matthias Brandli,
wireline communications has led to emerging standards in the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses (>20dB) [1], but their power consum
Christian Menolfi, Thomas Morf, Marcel Kossel, Lukas Kull, Danny Luu, M
ISSCC 2019 Session 30 Wireline I/O
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCOBased Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator
Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
generate low-jitter high-frequency signals, while using a ring VCO. In the sense that the VCO jitter is removed periodically by the reference clock, SREF, an MDLL also can be considered to be an ILCM. However, the most c
Ulsan National Institute of Science and Technology, Ulsan, Korea An in
ISSCC 2019 Session 30 Wireline I/O
A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM output current of the I-SSCP is zero, which means the sampled input differential voltage (VSAM+-VSAM-) is around 0V. At the same time, (VP+-VP-) is also around 0V, and both VP+ and VP- are kept almost constant regardless of the output frequency.
Zhao Zhang, Guang Zhu, C. Patrick Yue
To solve the issue of the conventional SSPD mentioned above, the LV SSPD (Fig. 30.8.3) is adopted. It adopts two high-level boosted inverters (HBINV) to enhance the turn-on voltage of the gate of M1 and M2 in the SSPD. T
ISSCC 2019 Session 30 Wireline I/O
An 8b Injection-Locked Phase Rotator with Dynamic Multiphase Injection for 28/56/112Gb/s Serdes Application
Yi-Chieh Huang, Bo-Jiun Chen
Growing traffic in data centers imposes multiple challenges on serial link design with higher speed and stringent power requirements. Clocking is one major challenge due to the significant portion of total power that clock
MediaTek, Hsinchu, Taiwan
ISSCC 2019 Session 30 Wireline I/O
A 6V Swing 3.6% THD >40GHz Driver with 4.5× Bandwidth Extension for a 272Gb/s Dual-Polarization 16-QAM Silicon Photonic Transmitter
Abdelrahman H. Ahmed1,2, Daihyun Lim2, Abdellatif Elmoznine2,
Yangjin Ma2, Tam Huynh2, Christopher Williams2, Leonardo Vera2, Yang Liu2, Ruizhi Shi2, Matthew Streshinsky2, Ari Novack2, Ran Ding2, Rick Younce2, Rafid Sukkar2, Jose Roman2, Michael Hochberg2, Sudip Shekhar1, Alexander
ISSCC 2019 Session 30 Wireline I/O
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS
Shayan Shahramian*1, Behzad Dehlaghi*1, Joshua Liang1,
Ryan Bespalko1, Dustin Dunwell1, James Bailey1, Bo Wang1, Alireza Sharif-Bakhtiar1, Michael O'Farrell1, Kerry Tang1, Anthony Chan Carusone2, David Cassan1, Davide Tonietto3 Huawei Technologies, Toronto, Canada University