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ISSCC 2021Session 8 · ULTRA-HIGH-SPEED WIRELINEWireline I/O7nm CMOS

An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS

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📋 论文概要

本文提出一种基于8位DAC的源串联终端(SST)发射器,采用金属栅电阻实现,在7nm CMOS工艺下达到112Gb/s PAM-4速率和1.4pJ/b的能效,并集成8抽头前馈均衡(FFE)。该设计解决了高速有线通信中对多调制格式支持和长信道均衡的需求,同时实现了高能效。

💡 主要创新点

核心指标
112Gb/s PAM-4, 1.4pJ/b能效, 8-Tap FFE
工艺节点
7nm CMOS
重要性
发表年份
ISSCC 2021

🏷 关键词

DAC基发射器SST发射器PAM-4前馈均衡FFE7nm CMOS金属栅电阻

📄 原文摘要

Thomas Morf1, Serdar A. Yonar1, Mridula Prathapan1, Eric J. Lukes2, Raymond A. Richetta2, Carrie Cox3 IBM Research, Rüschlikon, Switzerland IBM Systems and Technology, Rochester, MN 3 IBM Systems and Technology, Durham, NC 4 now with Samsung Semiconductor India Research, Bangalore 1 2 Digital-to-analog converter (DAC)-based transmitters are suited to support different modulation formats (e.g., NRZ, PAM-4, OFDM), long-channel equalization (incl. roaming taps) or even amplitude reduction for reflection mitigation at short channels. Compared to transmitters with a conventional FFE, a less complex and more uniform high-speed analog frontend can be designed in a DAC TX if the number of taps is large (e.g., >5) because the equalization is performed in the digital signal processing (DSP) unit running at sub-rate. However, this imposes the challenge of achieving low latency and power consumption, particularly at high resolution (e.g. 8b) and speed. The DAC TX presented

👥 作者与机构

Marcel A. Kossel1, Vishal Khatri1,4, Matthias Braendli1, Pier Andrea Francese1,

分类:Wireline I/O · 年份:ISSCC 2021