ISSCC 2021

2021

195 篇论文 · Wireline I/O (20) · RF & Wireless (18) · mm-Wave (17) · Digital Processors (16) · Data Converters (14)

ISSCC 2021 Session 10 Data Converters
A 116µW 104.4dB-DR 100.6dB-SNDR CT ΔΣ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter
Chilun Lo, Jongmi Lee, Yong Lim, Younghyun Yoon, Hyunseok Hwang,
applications because of its high energy efficiency and driving-friendly front-end compared with its discrete time counterpart. A resistive DAC (R-DAC) is widely used for its intrinsic low flicker noise. However, the desi
Jaehoon Lee, MooYeol Choi, Myungjin Lee, Seunghyun Oh, Jongwoo Lee Sam
ISSCC 2021 Session 10 Data Converters
A 139µW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs comparator non-idealities (e.g., signal-dependent delay) degrade the SQNR mostly in the main feedback path and not the auxiliary path. No extra fast path DAC or summing network is needed.
Somok Mondal1,2, Omid Ghadami1, Drew A. Hall1
The first integrator, shown in Fig. 10.2.3, is realized by a 4-stage amplifier with feedforward compensation. Two versions of the OTA, a 1- and 3-stack, were designed for comparison. For the tailless 3-stack version, the
ISSCC 2021 Session 10 Data Converters
A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer
Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn
Emerging communication and radar applications place enormous demands on ADC performance by requiring wide BW (100MHz) and high DR (70dB). Continuous-time delta-sigma modulators (CT-DSM) [1-2] are a mainstream solution as
University of Michigan, Ann Arbor, MI
ISSCC 2021 Session 10 Data Converters
A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR
Wei Shi1, Jiaxin Liu2, Abhishek Mukherjee1, Xiangxing Yang1, Xiyuan Tang1,
design suffers from a few challenges. First, it requires a large number of OTAs [1]. This increases the design complexity and power. In addition, each OTA contributes extra phase delay, whose reduction requires increasin
Linxiao Shen1, Wenda Zhao1, Nan Sun1,2 University of Texas, Austin, TX
ISSCC 2021 Session 10 Data Converters
A 12b 600MS/s Pipelined SAR and 2×-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET chip-to chip gain variation of the residue signal path. Moreover, the area-consuming 7b CDAC can be used in calibrating inter-stage offset error by adding offset in the feedback signal. Therefore, the comparator without offset calibration enables the SAR to enhance conversion speed.
Seungyeob Baek, Ilhoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim,
Youngjae Cho, Jongshin Shin Figure 10.5.3 shows the proposed adaptive speed-controlled (ASC) clock generation scheme. The ASC clock generator takes advantages from both the synchronous and asynchronous schemes by generat
ISSCC 2021 Session 10 Data Converters
A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET
Daniel Gruber*1, Martin Clara*2, Ramon Sanchez3, Yu-shan Wang4,
*Equally-Credited Authors (ECAs) Future multi-band software-defined-radio base-stations for digital beamforming and massive MIMO applications depend heavily on the availability of highly linear and compact data converter
Christoph Duller1, Gerald Rauter1, Patrick Torta1, Kamran Azadet2 Inte
ISSCC 2021 Session 10 Data Converters
A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters
Martin Clara*1, Daniel Gruber*2, Albert Molina3, Matteo Camponeschi2,
Yu-shan Wang4, Christian Lindholm2, Hundo Shin5, Ramon Sanchez3, Christoph Duller2, Patrick Torta2, Kamran Azadet1 Intel, Santa Clara, CA Intel, Villach, Austria 3 Intel, Madrid, Spain 4 Intel, Hillsboro, OR 5 now with A
ISSCC 2021 Session 11 Wireline I/O
A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology
Ramy Yousry*1, Ehung Chen*1, Yu-Ming Ying1, Mohammed Abdullatif1,
Mohammad Elbadry1, Ahmed ElShater1, Tsz-Bin Liu2, Joonyeong Lee1, Dhinessh Ramachandran1, Kaiz Wang2, Chih-Hao Weng2, Mau-Lin Wu2, Tamer Ali1 MediaTek, Irvine, CA MediaTek, Hsinchu, Taiwan 1 2 *Equally-Credited Authors (
ISSCC 2021 Session 11 Wireline I/O
A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS
Ravi Shivnaraine1, Marcus van Ierssel1, Kamran Farzan1, Dominic Diclemente1,
George Ng1, Nanyan Wang2, Javid Musayev1, Gairik Dutta1, Masumi Shibata1, Arash Moradi1, Haleh Vahedi1, Manavi Farzad1, Prabhnoor Kainth1, Matt Yu1, Nhat Nguyen2, Jennifer Pham1, Angus McLaren1 Rambus, Toronto, Canada Ra
ISSCC 2021 Session 11 Wireline I/O
A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications
Kelvin McCollough, Scott D. Huss, James Vandersand, Randall Smith,
Chris Moscone, Qazi Omar Farooq Cadence, Cary, NC With recent AI and big data developments, quickly moving massive amounts of data is paramount to future technologies. Scalable solutions that can sustain higher performan
ISSCC 2021 Session 11 Wireline I/O
A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links
Zhaowen Wang*, Yudong Zhang*, Yuka Onizuka, Peter R. Kinget
*Equally-Credited Authors (ECAs) The ever-increasing Internet data demand imposes stringent requirements on wireline transceiver speed, jitter, and power. A low-noise, multi-phase clock generator (MPCG) is a crucial buil
Columbia University, New York, NY
ISSCC 2021 Session 11 Wireline I/O
A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET
Dongseok Shin, Hyung Seok Kim, Chuan-chang Liu, Priya Wali,
100Gb/s+ is rapidly increasing to accommodate the massive data traffic of data centric systems such as Internet-of-things, autonomous driving, cloud computing, etc. In recent publications, a 14GHz LC-PLL was successfully
Savyasaachi Keshava Murthy, Yongping Fan Intel, Hillsboro, OR Interest
ISSCC 2021 Session 11 Wireline I/O
A 100Gb/s -8.3dBm-Sensitivity PAM-4 Optical Receiver with
Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS
g. 400G-DR4/FR4) have been developed to address the rapid increase in interconnect BW demand created by data-centric computing [1]. Low-cost 100Gb/s PAM-4 optical transceivers are critical to spur their adoption in high
Hao Li, Jahnavi Sharma, Chun-Ming Hsu, Ganesh Balamurugan, James Jauss
ISSCC 2021 Session 11 Wireline I/O
A 56Gb/s 50mW NRZ Receiver in 28nm CMOS
Atharav Atharav, Behzad Razavi
The power consumption of wireline transceivers has become increasingly critical as higher data rates and a larger numbers of lanes per chip are sought [1-6]. While attractive for lossy channels, PAM-4 signaling has mostl
University of California, Los Angeles, CA
ISSCC 2021 Session 11 Wireline I/O
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS
Ramin Farjadrad1, Kambiz Kaviani1, David Nguyen1, Michael Brown1,
Govert Geelen2, Corné Bastiaansen2, Narendra Rao1, Viswa Popuri1, Greg Shen1, Hamid Khatibi1, Saudas Dey3, Anirban Chatterjee3, David Shen1, Peter Zijlstra2, Harrie Gunnink2, Kebin Zhang1, Venkat Penumuchu1, Oliver Weiss
ISSCC 2021 Session 11 Wireline I/O
A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler
Jack W. Holloway1,2, Georgios C. Dogiamis3, Ruonan Han1
Raytheon, Tewksbury, MA 3 Intel, Chandler, AZ 1 The rapid surge of data transmission within computation, storage and communication infrastructures is pushing the speed boundary of traditional copper-based electrical link
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2021 Session 12 AI / ML
A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network
Zhixuan Wang1, Le Ye1,2, Ying Liu1, Peng Zhou2, Zhichao Tan3, Haitao Fan2,
University, Hangzhou, China 4 XINYI Information Technology, Shanghai, China 1 2 Power is a major bottleneck in AIoT devices, which usually operate in random-sparseevent (RSE) scenarios [1] (Fig. 12.1.1, bottom). To proce
Yihan Zhang1, Jiayoon Ru4, Yangyuan Wang1, Ru Huang1 Peking University
ISSCC 2021 Session 12 Power Management
Improving the Range of WiFi Backscatter Via a Passive Retro-Reflective Single-Side-Band-Modulating MIMO Array and Non-Absorbing Termination
Miao Meng1, Manideep Dunna1, Hans Yu1, Shihkai Kuo1, P-H. P. Wang1,2,
Dinesh Bharadia1, Patrick P. Mercier1 University of California San Diego, La Jolla, CA Broadcom, San Diego, CA 1 2 Wi-Fi is the most ubiquitous wireless networking technology for IoT in homes, offices, and businesses. Si
ISSCC 2021 Session 12 Power Management
Exploring PUF-Controlled PA Spectral Regrowth for Physical-Layer Identification of IoT Nodes
Qiang Zhou*, Yan He*, Kaiyuan Yang, Taiyun Chi
*Equally-Credited Authors (ECAs) It is projected that 75 billion Internet-of-Things (IoT) devices will be deployed for applications such as wearable electronics and smart home by 2025. Securing IoT devices is one of the
Rice University, Houston, TX
ISSCC 2021 Session 13 Quantum & Photonics
A Fully Integrated Cryo-CMOS SoC for Qubit Control in
Quantum Computers Capable of State Manipulation, Readout
FFL FinFET Technology Jong-Seok Park1, Sushil Subramanian1, Lester Lampert1, Todor Mladenov1, Ilya Klotchkov1, Dileep J. Kurian2, Esdras Juarez-Hernandez3, Brando Perez-Esparza3, Sirisha Rani Kale1, Asma Beevi K. T. 4, S
and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm
ISSCC 2021 Session 13 Quantum & Photonics
A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-onChip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots
Andrea Ruffino*1, Yatao Peng*1, Tsung-Yeh Yang2, John Michniewicz3,
Quantum Motion Technologies, Leeds, United Kingdom differential-to-single-ended buffer for 50Ω output match. The LO signal for downconversion is generated on chip by an analog charge-pump integer-N PLL with a programmabl
Miguel Fernando Gonzalez-Zalba2,4, Edoardo Charbon1 EPFL, Neuchâtel, S
ISSCC 2021 Session 13 Quantum & Photonics
A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS Technology
Bagas Prabowo1,2, Guoji Zheng1,2, Mohammadreza Mehrpoo1,3, Bishnu Patra1,2,
Patrick Harvey-Collard1,2, Jurgen Dijkema1,2, Amir Sammak4, Giordano Scappucci1,2, Edoardo Charbon1,2,5, Fabio Sebastiano1,2, Lieven M. K. Vandersypen1,2, Masoud Babaie1,2 Delft University of Technology, Delft, The Nethe
ISSCC 2021 Session 13 Quantum & Photonics
A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS
Gerd Kiene1,2, Alessandro Catania3, Ramon Overwater1,2, Paolo Bruschi3,
Italy 4 EPFL, Neuchatel, Switzerland 1 2 Quantum computers (QCs) promise significant speedup for relevant computational problems that are intractable by classical computers. QCs process information stored in quantum bits
Edoardo Charbon1,2,4, Masoud Babaie1,2, Fabio Sebastiano1,2 Delft Univ
ISSCC 2021 Session 14 mm-Wave
A 71-to-86GHz Packaged 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver in 28nm CMOS
Emily Naviasky, Lorenzo Iotti, Greg LaCaille, Borivoje Nikolić, Elad Alon, Ali Niknejad
high-capacity wireless access. A base-station array of M antennas simultaneously steers K independent beams, which enables spatial multiplexing and channel bandwidth reuse across multiple users. It has been shown that fo
University of California, Berkeley, CA Multi-User MIMO (MU-MIMO) at mm
ISSCC 2021 Session 14 mm-Wave
An Early Fusion Complementary RADAR-LiDAR TRX in 65nm CMOS Supporting Gear-Shifting Sub-cm Resolution for Smart Sensing and Imaging
Liheng Lou1, Kai Tang1, Zhongyuan Fang1, Yisheng Wang2, Bo Chen1, Ting Guo1,
sensing provides comprehensive and effective environment information through complementary signals in data acquisition. As an emerging solution, the multimodal sensing becomes essential and boosts applications in automot
Xiaohua Feng1, Siyu Liu1, Wensong Wang1, Yuanjin Zheng1 Nanyang Techno
ISSCC 2021 Session 14 mm-Wave
A 26GHz Full-Duplex Circulator Receiver with 53dB/400MHz (40dB/800MHz) Self-Interference Cancellation for mm-Wave Repeaters
Robin Garg, Sanket Jain, Paul Dania, Arun Natarajan
Reduction in base-station deployment costs while increasing coverage has motivated Integrated Access and Backhaul (IAB) nodes in mm-wave 5G NR (Fig. 14.3.1). Similarly, high path loss due to shadowing and limited outdoor
Oregon State University, Corvallis, OR
ISSCC 2021 Session 14 mm-Wave
A 24-to-30GHz Double-Quadrature Direct-Upconversion Transmitter with Mutual-Coupling-Resilient Series-Doherty Balanced PA for 5G MIMO Arrays
Masoud Pashaeifar, Leo C. N. de Vreede, Morteza S. Alavi
The performance and robustness of millimeter-wave (mm-wave) phased-array transmitters (TXs) define, to a large extent, the quality of a high-data-rate 5G link. In practical situations, however, this TX performance is str
Delft University of Technology, Delft, The Netherlands
ISSCC 2021 Session 14 mm-Wave
A 1V W-Band Bidirectional Transceiver Front-End with <1dB
T/R Switch Loss, <1°/dB Phase/Gain Resolution and 12.3%
Wei Zhu, Jiawen Wang, Ruitao Wang, Yan Wang Institute of Microelectronics of Tsinghua University, Beijing, China Millimeter-wave (mm-wave) imaging radars and communication systems operating at W-band obtain an ever-incre
TX PAE at 15.1dBm Output Power in 65nm CMOS Technology
ISSCC 2021 Session 14 mm-Wave
A 76-to-81GHz 2×8 FMCW MIMO Radar Transceiver with Fast Chirp Generation and Multi-Feed Antenna-in-Package Array
Zongming Duan1, Bowen Wu1, Chuanming Zhu1, Yan Wang1, Weiwei Jin1,
Ying Liu1, Yanhui Wu2, Tao Zhang2, Ming Liu1, Bingfei Dou1, Bingbing Liao1, Wei Lv1, Dongfang Pan3, Yongjie Li3, Changwei Wang3, Yuefei Dai1, Pei Li1, Hao Gao4,5 East China Research Institute of Electronic Engineering, H
ISSCC 2021 Session 14 mm-Wave
An Adaptive Analog Temperature-Healing Low-Power 17.7-to-19.2GHz RX Front-End with ±0.005dB/°C
Gain Variation, <1.6dB NF Variation, and <2.2dB IP1dB, Variation across -15 to 85°C for Phased-Array Receiver
Min Li*1, Nayu Li*1, Huiyan Gao*1, Shaogang Wang*1, Zijiang Zhang1, Peidi Chen1, Ningjie Wei1, Qun Jane Gu2, Chunyi Song1, Zhiwei Xu1 Zhejiang University, Zhoushan, China University of California, Davis, CA 1 2 *Equally-
ISSCC 2021 Session 14 mm-Wave
A Fully Integrated 62-to-69GHz Crystal-Less Transceiver with 12 Channels Tuned by a Transmission-LineReferenced FLL in 0.13µm BiCMOS
Jaeho Im, Hyeongseok Kim, Omar Abdelatty, David D. Wentzloff
The progress towards smaller Wireless Sensor Networks (WSNs) has expanded the applications for ubiquitous sensing. However, the form-factor of a WSN is typically limited by bulky off-chip components, mainly the crystal r
University of Michigan, Ann Arbor, MI
ISSCC 2021 Session 15 AI / ML
A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing operations occur in the dedicated NMC BPBS SIMD module, which is optimized for 1-to-8b weights/activations, and further programmable element-wise operations (e.g., arbitrary activations functions) occur in the NMC CMPT SIMD module.
Hongyang Jia, Murat Ozatay*, Yinqi Tang*, Hossein Valavi*, Rakshit Pathak*,
Jinseok Lee, Naveen Verma Figure 15.1.3 shows a sample of the operations enabled by CIMU configurability and the SW instruction libraries. In addition to temporal mapping of NN layers, the architecture provides extensive
ISSCC 2021 Session 15 Digital Processors
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
Jinshan Yue1,2, Xiaoyu Feng1, Yifan He1, Yuxuan Huang1, Yipeng Wang2,
Zhe Yuan1, Mingtao Zhan1, Jiaxin Liu1, Jian-Wei Su3, Yen-Lin Chung3, Ping-Chun Wu3, Li-Yang Hung3, Meng-Fan Chang3, Nan Sun1, Xueqing Li1, Huazhong Yang1, Yongpan Liu1 Tsinghua University, Beijing, China Pi2star Technolo
ISSCC 2021 Session 15 AI / ML
A 65nm 3T Dynamic Analog RAM-Based Computing-inMemory Macro and CNN Accelerator with Retention
Enhancement, Adaptive Analog Sparsity and 44TOPS/W, System Energy Efficiency
computing inside memory macros have shown significant advantages in computing efficiency for deep learning applications. While earlier CIM macros were limited by lower bit precision, e.g. binary weights in [1], recent wo
Zhengyu Chen, Xi Chen, Jie Gu Northwestern University, Evanston, IL Co
ISSCC 2021 Session 15 Digital Processors
A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization
balancing. In each macro, 16 VGBLs and 8 HGBLs are activated simultaneously. 2 TCs, are divided into tiles. Each tile ha
position of M macros. The CMA reduces memory accesses by 70.32%, on average, in various NNs. Ruiqi Guo1, Zhiheng Yue1, Xin Si2, Te Hu1, Hao Li1, Limei Tang1, Yabing Wang1, Leibo Liu1, Meng-Fan Chang3, Qiang Li2, Shaojun
ISSCC 2021 Session 16 Memory
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices
Cheng-Xin Xue*1, Je-Min Hung*1, Hui-Yao Kao1, Yen-Hsiang Huang1,
Sheng-Po Huang1, Fu-Chun Chang1, Peng Chen1, Ta-Wei Liu1, Chuan-Jia Jhang1, Chin-I Su2, Win-San Khwa2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Yu-Der Chih2, Tsung-Yung Jonathan Chang2, Meng-Fa
ISSCC 2021 Session 16 AI / ML
eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing
Shanshan Xie1, Can Ni1, Aseem Sayal1, Pulkit Jain2, Fatih Hamzaoglu2, Jaydeep P. Kulkarni1
has led to massive amounts of data movement from off-chip memory to on-chip processing cores in modern machine learning (ML) accelerators. Compute-in-memory (CIM) designs performing analog DNN computations within a memor
University of Texas, Austin, TX Intel, Hillsboro, OR 1 2 The unprecede
ISSCC 2021 Session 16 Memory
A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips VGBL= (VMM15 × CGBL15 + VMM14 × CGBL14 + … + VMM0 × CGBL0)/(CGBL15 + CGBL14 + … + CGBL0). The voltage of GBLB (VGBLB) is the pMACV of 2bIN×1bW with 16-channel accumulation using the LSB part of a 4b-input (IN10).
Jian-Wei Su*1,2, Yen-Chi Chou*1, Ruhui Liu1, Ta-Wei Liu1, Pei-Jung Lu1,
Ping-Chun Wu1, Yen-Lin Chung1, Li-Yang Hung1, Jin-Sheng Ren1, Tianlong Pan1, Sih-Han Li2, Shih-Chieh Chang2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Chih-I Wu2, Xin Si1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-T
ISSCC 2021 Session 16 Memory
An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications
Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee,
Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Ch
ISSCC 2021 Session 17 Power Management
A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating 0.6V/µs Input Slew Rate During Startup
Ziyu Xia, Jason Stauth
Efficient high-conversion-ratio power delivery is needed for many portable computing applications which require sub-volt supply rails but operate from batteries or USB power sources. In such applications, the power manag
Dartmouth College, Hanover, NH
ISSCC 2021 Session 17 Power Management
A Masterless Fault-Tolerant Hybrid Dickson Converter with 95.3% Peak Efficiency 20V-to-60V Input and 3.3V Output for 48V Multi-Phase Automotive Applications
Mojtaba Ashourloo1, Venkata Raghuram Namburi1, Gerard Villar Piqué2,
NXP Semiconductors, Chandler, AZ 1 Autonomous-driving features have increased the load power demand of processors, which in turn, have resulted in the development of a 48V bus in electric vehicles. The resulting high and
John Pigott3, Henk Jan Bergveld2, Alaa El Sherif3, Olivier Trescases1
ISSCC 2021 Session 17 Power Management
A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
Alessandro Novello1, Gabriele Atzeni1, Giorgio Cristiano1, Mathieu Coustans2, Taekwang Jang1
electronics has strengthened the demand for fully integrated power management circuits. Buck converters offer high efficiency, but they cannot satisfy the stringent size requirements because bulky off-chip inductors are
ETH Zurich, Zurich, Switzerland STMicroelectronics, Plan-les-Ouates, S
ISSCC 2021 Session 17 Power Management
Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing
Nachiket Desai1, Harish K. Krishnamurthy1, Khondker Ahmed1, Sheldon Weng1,
Suhwan Kim1, Xiaosen Liu1, Huong T. Do2, Kaladhar Radhakrishnan2, Krishnan Ravichandran1, James W. Tschanz1, Vivek De1 Intel, Hillsboro, OR Intel, Chandler, AZ 1 2 High-performance many-core processors and GPUs demand 10
ISSCC 2021 Session 17 Power Management
A 98.2%-Efficiency Reciprocal Direct Charge Recycling Inductor-First DC-DC Converter
Abdullah Abdulslam, Patrick P. Mercier
Inductive DC-DC converters are fundamentally limited by the trade-off between conduction losses and switching losses. Miniaturized converters used in applications such as mobile devices suffer badly from this trade off,
University of California, San Diego, La Jolla, CA
ISSCC 2021 Session 17 Power Management
A Reconfigurable DC-DC Converter for Maximum TEG Energy Harvesting in a Battery-Powered Wireless Sensor Node
Young-Seok Noh, Jeong-Il Seo, Won-Jong Choi, Ji-Hwan Kim,
wireless sensor node (WSN). However, energy harvesting resources are inherently sporadic and critically affected by their environment, mandating energy storage elements (e.g., battery or super-capacitor) to guarantee a r
Hoang Van Phuoc, Hyun-Sik Kim, Sang-Gug Lee KAIST, Daejeon, Korea Ener
ISSCC 2021 Session 17 Power Management
A 0.03mV/mA Low Crosstalk and 185nA Ultra-Low-Quiescent Single-Inductor Multiple-Output Converter Assisted by 5-Input Operational Amplifier for 94.3% Peak Efficiency and 3.0W Driving Capability
Tzu-Hsien Yang1, Yong-Hwa Wen1, Yu-Jheng Ouyang1, Chun-Kai Chiu1,
multi-output (SIMO) converter offers the advantage of small size and can provide distributive voltage/current for wearable electronic devices. However, there are still some design challenges to solve. In continuous-condu
Bo-Kuan Wu1, Ke-Horng Chen1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen T
ISSCC 2021 Session 17 Power Management
A 90.5%-Efficiency 28.7µVRMS-Noise Bipolar-Output HighStep-Up SC DC-DC Converter with Energy-Recycled Regulation and Post-Filtering for ±15V TFT-Based LAE Sensors
Min-Woo Ko, Hyunki Han, Hyun-Sik Kim
The applications of large-area electronics (LAEs) based on thin-film transistors (TFTs) are rapidly expanding from displays to sensors. For the TFT gate drivers, high-voltage bipolar supply rails (approximately ±15V) are
KAIST, Daejeon, Korea
ISSCC 2021 Session 17 Power Management
A High-Conversion-Ratio and 97.4% Peak-Efficiency 3-Switch Boost Converter with Duty-Dependent Charge Topology for 1.2A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED Applications
Yen-An Lin1, Si-Yi Li1, Zheng-Lun Huang1, Chong-Sin Huang1,
Chin-Hsiang Liang1, Kai-Syun Chang1, Kai-Cheng Chung1, Ke-Horng Chen1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen Tsai2 National Chiao Tung University, Hsinchu, Taiwan, Realtek Semiconductor, Hsinchu, Taiwan 1 2 Today’s min
ISSCC 2021 Session 18 Medical & Bio
An Optically-Addressed Nanowire-Based Retinal Prosthesis with 73% RF-to-Stimulation Power Efficiency and 20nC-to-3µC Wireless Charge Telemetering
Abraham Akinin1, Jeremy M. Ford1, Jiajia Wu1, Chul Kim2, Hiren D. Thacker3,
Patrick P. Mercier1, Gert Cauwenberghs1 University of California, San Diego, La Jolla, CA KAIST, Daejeon, Korea 3 Nanovision Biosciences, San Diego, CA 1 2 Recent approaches toward a functional retinal prosthesis to rest
ISSCC 2021 Session 18 Medical & Bio
CMOS-Driven Pneumatic-Free Scalable Microfluidics and Fluid Processing with Label-Free Cellular and Bio-Molecular Sensing Capability for an End-to-End Point-of-Care System
Chengjie Zhu, Jesus Maldonado, Hao Tang, Suresh Venkatesh, Kaushik Sengupta
point-of-care (POC) molecular diagnostic platforms that encompass an end-to-end system (from sample fluid to diagnostic information) with the ability to allow rapid analysis on the spot. While POC sensing technologies ha
Princeton University, Princeton, NJ The emergence of the pandemic has