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ISSCC 2021Session 11 · ADVANCED WIRELINE LINKS AND TECHNIQUESWireline I/O14nm CMOS

An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS

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📋 论文概要

本文提出了一种用于112Gb/s PAM-4同时双向信令的回声消除前端,采用14nm CMOS工艺,旨在满足超大规模数据中心对高速、低延迟数据连接的需求。该设计通过创新的回声消除技术解决了双向信令中的自干扰问题,实现了高数据速率传输。

💡 主要创新点

核心指标
112Gb/s PAM-4
工艺节点
14nm CMOS
重要性
发表年份
ISSCC 2021

🏷 关键词

回声消除PAM-4同时双向信令14nm CMOS高速有线通信

📄 原文摘要

Govert Geelen2, Corné Bastiaansen2, Narendra Rao1, Viswa Popuri1, Greg Shen1, Hamid Khatibi1, Saudas Dey3, Anirban Chatterjee3, David Shen1, Peter Zijlstra2, Harrie Gunnink2, Kebin Zhang1, Venkat Penumuchu1, Oliver Weiss1, Edward Paulus2, Joost Briaire2 Marvell, Santa Clara, CA Marvell, Eindhoven, The Netherlands 3 Marvell, Bangalore, India 1 2 The rapid growth of hyperscale data centers has led to an increased demand for highspeed and low-latency data connectivity solution upgrades, which are power-efficient and minimal cost. In the last few years, PAM-4 modulation across copper channels was realized by high-performance electrical transceivers in a tight signal integrity environment, which employed the superior spectral efficiency of PAM-4 over NRZ signaling. This shift created a relatively smooth path from 28Gb/s NRZ to 56Gb/s PAM4 per lane by keeping the same baud rate, which eliminated the need to replace the

👥 作者与机构

Ramin Farjadrad1, Kambiz Kaviani1, David Nguyen1, Michael Brown1,

分类:Wireline I/O · 年份:ISSCC 2021