A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth

📋 论文概要

本文提出了一种采用32kHz参考频率的分数-N过采样锁相环(OSPLL)，通过DAC和DTC辅助技术实现200kHz环路带宽和5.79ps rms抖动，解决了传统32kHz参考PLL因窄环路带宽而导致的抖动性能下降问题。

💡 主要创新点

• 采用DAC和DTC辅助的过采样架构，使得PLL能够以32kHz参考频率实现200kHz的高环路带宽，突破了传统限制。
• 通过过采样技术，在不增加参考频率的情况下显著提升PLL的带宽和抖动性能。

🏷 关键词

📄 原文摘要

independent crystal oscillators (XOs): a 32.768kHz XO for the real-time clock (RTC) and a tens of MHz XO for low-jitter clock and carrier synthesis. To reduce the number of XOs, 32kHz-reference phase-locked loops (PLLs) [1,2] have been reported. However, the jitter performance is degraded due to narrow loop bandwidth, e.g., less than 3kHz, limited by the 32kHz reference frequency. To break this limitation, a 2.4GHz fractional-N oversampling PLL (OSPLL) with a 32kHz reference is proposed in this paper. The proposed DAC- and DTCassisted OSPLL realizes a 200kHz loop bandwidth and 5.79ps rms jitter with 4.97mW power consumption in a 65nm CMOS technology. Figure 32.7.1 explains the features of the proposed OSPLL as compared with a

👥 作者与机构

Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian,

Hongye Huang, Yuncheng Zhang, Yun Wang, Atsushi Shirane, Kenichi Okada Tokyo Institute of Technology, Tokyo, Japan Low-power internet-of-things (IoT) devices sometimes use two