A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter

📋 论文概要

该论文提出了一种12.9-15.1GHz的数字锁相环（DPLL），采用bang-bang鉴相器并引入自适应优化噪声整形技术，有效抑制了量化噪声和极限环效应，实现了低抖动高性能频率合成。

💡 主要创新点

• 提出自适应优化噪声整形（ASC）方法，通过监视自相关函数符号自动调节延迟量，使S-BBPD工作在最佳噪声整形状态，避免参数失配。
• 在宽带DPLL中首次实现bang-bang鉴相器与自适应噪声整形的结合，在12.9-15.1GHz频段内同时实现低带内噪声和快速锁定。

🏷 关键词

📄 原文摘要

Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Andrea Leonardo Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy University College Dublin, Dublin, Ireland filtering of the DPLL time error; for ∆tq = τopt, ρ[m] is almost impulsive; and for ∆tq > τopt, an oscillating ρ[m] is observed, which is coherent with the rise of limit cycles in the S-BBPD. To identify the optimum condition, the ASC accumulates an odd sample of the autocorrelation (ρ[3], in this case), whose sign depends on the ∆tq-to-τopt ratio and applies the sum to the delay control. At convergence, the average accumulator input has to be zero, thus resulting in ρ[3] = 0 and, in turns, ∆tq = τopt. Fine-bank saturation is dealt with by rippling the carry to another accumulator controlling the coarse delay. It is worth to point out that the first autocorrelation sample ρ[1] is deliberately not used

👥 作者与机构

Mario Mercandelli*1, Alessio Santiccioli*1, Simone Mattia Dartizio*1,

Abanob Shehata1, Francesco Tesolin1, Saleh Karman1, Luca Bertulessi1,