A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

📋 论文概要

本文提出了一款24Gb/s/pin的8Gb GDDR6 DRAM，采用半速率菊花链时钟架构和低噪声IO电路，解决了高速数据传输中的时钟抖动和噪声问题，实现了超过18Gb/s/pin的数据速率。

💡 主要创新点

• 提出半速率菊花链时钟架构，降低时钟分布路径上的抖动和功耗。
• 设计低噪声IO电路，包括改进的接收器和输出驱动器，减少信号完整性问题。
• 通过优化片内终端和均衡技术，支持24Gb/s/pin的高速操作。

🏷 关键词

📄 原文摘要

Sangyeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park , Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee , Junhyun Chun, Hyungsoo Kim, Seonyong Cha SK hynix Semiconductor, Icheon, Korea The demand for high-performance graphics systems used for artificial intelligence continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. Enabling GDDR6 DRAM to achieve data rates beyond 18Gb/s/pin [1] requires identifying and solving factors that affect the speed of a memory interface. Prior studies have showed that the memory interface is vulnerable from the signal integrity (SI) and power integrity (PI) perspective, since it is based on a parallel interface using single-ended signaling. Furthermore, circuit schemes to mitigate process, voltage, and

👥 作者与机构

Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gangsik Lee,