A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS

📋 论文概要

本文提出了一种单电感四输出SoC，通过动态压降分配和自适应时钟技术，解决了单电感多输出转换器瞬态响应差和纹波大的问题，从而提升系统性能和能效。

💡 主要创新点

• 提出动态压降分配（Dynamic Droop Allocation）技术，根据负载需求动态调整各输出域的电压裕量，减少不必要的功耗。
• 引入自适应时钟（Adaptive Clocking）机制，根据实际电压波动调整时钟频率，避免因电压下降导致的时序错误，同时降低电压裕量需求。
• 实现单电感四输出SoC，在共享单个电感的情况下提供多个精细供电域，减少无源元件数量，同时保持接近buck转换器的效率。

🏷 关键词

📄 原文摘要

University of Washington, Seattle, WA Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (Vdd) domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1–5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive Vdd margining. Operation at an elevated Vdd—and, therefore, the load-current (Iload)—inflates power draw and further reduces system efficiency (ηsystem), i.e. the ratio of the useful (margin-free) output power to input power draw. Recently reported SIMO architectures have demonstrated significant transient response improvement. In [1], low-dropout (LDO) regulators are placed in series with voltage domains. Cross-regulation in SIMO designs, a phenomenon where transient loading in

👥 作者与机构

Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe