An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS

📋 论文概要

该论文提出了一种在28nm CMOS工艺中实现的200Gb/s PAM-4和100Gb/s NRZ发射机，通过最小化驱动器电容、采用灵活时钟时序控制的复用技术以及全可重构5抽头FFE架构，显著提升了输出带宽和摆幅，解决了超高速互连中的信号完整性问题。

💡 主要创新点

• 通过pull-up电流源最小化驱动器电容，提高了输出带宽和摆幅。
• 采用灵活的时钟时序控制实现多路复用，优化了高速信号时序。
• 设计了全可重构的5抽头FFE架构，支持PAM-4和NRZ模式的自适应均衡。

🏷 关键词

📄 原文摘要

for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1-4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by minimizing the driver capacitance with pull-up current sources, multiplexing with flexible clock timing control, and employing a fully reconfigurable 5-tap FFE architecture. Figure 8.2.1 shows the overall TX architecture. The TX receives external differential 25GHz clocks (C4P/N) that drive an injection-locked quadrature clock generator. Dutycycle distortion and quadrature errors are compensated by dedicated duty-cycle and quadrature timing adjustment circuits. The 4-phase 25GHz clocks (C4I/Q) are distributed

👥 作者与机构

Minsoo Choi*1, Zhongkai Wang*1, Kyoungtae Lee1, Kwanseo Park1,

Zhaokai Liu1, Ayan Biswas1, Jaeduk Han2, Elad Alon1 University of California, Berkeley, CA Hanyang University, Seoul, Korea 1 2 *Equally-Credited Authors (ECAs) The ever-expanding demand