A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET

📋 论文概要

本文提出了一种用于224Gb/s有线通信的23.9-29.4GHz数字LC-PLL，采用耦合倍频器实现频率加倍，在10nm FinFET工艺下实现了低抖动和低功耗。解决了高速数据率下PLL时钟频率加倍带来的抖动和功耗挑战。

💡 主要创新点

• 提出耦合倍频器结构，在不显著增加抖动和功耗的前提下将PLL输出频率从14GHz倍增至28GHz。
• 采用全数字LC-PLL架构，结合宽调谐范围（23.9-29.4GHz），适应不同数据速率需求。

🏷 关键词

📄 原文摘要

100Gb/s+ is rapidly increasing to accommodate the massive data traffic of data centric systems such as Internet-of-things, autonomous driving, cloud computing, etc. In recent publications, a 14GHz LC-PLL was successfully demonstrated for 112Gb/s PAM-4 transmitter clocking [1-3]. To extend the data rate to 224Gb/s, a 28GHz LC-PLL can be adopted instead of increased interleaving or use of higher-order modulation (PAM-8/16). However, doubling the PLL clock frequency without jitter or power penalties is challenging because doubling the data rate requires a 50% jitter reduction while CML-to-CMOS buffer and prescaler divider have increasing power overhead as they are pushed closer to millimeter-wave (mm-wave) frequency ranges. This paper presents a 23.9-to-29.4GHz digital LC-PLL

👥 作者与机构

Dongseok Shin, Hyung Seok Kim, Chuan-chang Liu, Priya Wali,

Savyasaachi Keshava Murthy, Yongping Fan Intel, Hillsboro, OR Interest in ultra-high-speed wireline communications targeting