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ISSCC 2021Session 11 · ADVANCED WIRELINE LINKS AND TECHNIQUESWireline I/O65nm

A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文提出了一种基于注入锁定技术的多相时钟发生器,工作在7GHz,可产生8相时钟,并集成7位相位插值器,用于高速有线通信系统中的时钟恢复和相位调整。该设计在65nm工艺下实现了高精度和低噪声性能,解决了传统多相时钟发生器在频率和相位误差补偿方面的挑战。

💡 主要创新点

工艺节点
65nm
重要性
发表年份
ISSCC 2021

🏷 关键词

注入锁定多相时钟发生器相位插值器有线通信时钟恢复

📄 原文摘要

*Equally-Credited Authors (ECAs) The ever-increasing Internet data demand imposes stringent requirements on wireline transceiver speed, jitter, and power. A low-noise, multi-phase clock generator (MPCG) is a crucial building block in both forwarded-clock and clock-data-recovery (CDR) based clocking systems (Fig. 11.4.1). In CDR-based systems, a global phase-locked loop generates a low-noise, differential clock and distributes it to each lane, where a local phase adjuster, consisting of a multi-phase clock generator and phase interpolators (PIs), compensates the frequency and phase errors between the incoming data and quadrature clocks; while in a forwarded-clock system, the forwarded clock from the transmitter is adjusted by a delay line for phase deskew and the MPCG generates multiple phases for the ADCs. Multi-phase injection-locked ring oscillators (MPILOSCs) [1,2] provide accurate, low-noise, multi-phase clocks thanks to their wide locking range and

👥 作者与机构

Zhaowen Wang*, Yudong Zhang*, Yuka Onizuka, Peter R. Kinget

Columbia University, New York, NY

分类:Wireline I/O · 年份:ISSCC 2021