A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-CellBased Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

📋 论文概要

本文提出了一种基于5nm工艺的数字型SRAM宏单元，采用16T位单元支持位写掩码操作，解决了传统SRAM在最小工作电压和面积效率上的问题。通过采用标准单元规则设计布局，实现了在1.0V下5.7GHz和0.5V下1.3GHz的工作频率。

💡 主要创新点

• 提出16T位单元支持位写掩码操作，避免了半选择问题。
• 采用标准单元规则设计SRAM布局，提高了面积效率并减少了鳍边界处的空白区域。

🏷 关键词

📄 原文摘要

the minimum operating voltage (VMIN). Furthermore, fin formation differences between the SRAM bitcells, the peripheral circuits and the standard logic degrade area efficiency due to the empty spaces at fin-to-fin boundary and the required dummy [1]. Memories with small capacities that use the classical SRAM design suffer from this issue the most. In this paper, we will propose a 5nm digital-based SRAM macro with a 16T cell supporting a bit-write-mask operation. We adopted the standard cell rules for the proposed SRAM layout design. The area of the 16T cell is larger than the foundry’s 6T SRAM cell; however, the total macro area of a small capacity SRAM is smaller since there is no empty space in the macro and due to its simple peripheral circuit. In addition, the

👥 作者与机构

Hidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu,

Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang TSMC, Hsinchu, Taiwan Continued scaling of the transistor increases random Vt variation, which limits