A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver

📋 论文概要

本文提出一种滑窗判决反馈均衡器（SB-DFE）架构，在7nm FinFET工艺上实现了112Gb/s PAM-4线缆接收机中的9抽头低功耗DFE，通过流水线化解决了传统DFE因时序闭合限制仅能实现1-2抽头的难题。

💡 主要创新点

• 提出滑窗DFE（SB-DFE）架构，利用流水线技术打破了传统DFE抽头数受时序闭合限制的壁垒。
• 在7nm FinFET工艺下实现了112Gb/s PAM-4速率的9抽头DFE，兼具低功耗特性。

🏷 关键词

📄 原文摘要

equalization (e.g. extensive FFE and DFE) of wireline channels. FFE and canonical DFE sizes scale linearly with the number of taps, however the computational complexity of an FFE is much greater than that of a DFE. The canonical DFE is challenged by timing closure, and necessary techniques to ease it result in exponential growth in size. As a result, the majority of state-of-the-art DFE implementations have been limited to only 1-2 taps [1-4]. In this paper, a slidingblock DFE (SB-DFE) is introduced that enables pipelining and breaks the barrier to implementing much longer DFEs. Consequently, the DFE length can be extended to encompass all postcursors. Unlike FFEs, DFEs do not amplify noise. Moreover, a long DFE can relax or even remove the postcursor equalization burden on the CTLE and FFE,

👥 作者与机构

James Bailey1, Hossein Shakiba1, Ehud Nir2, Grigory Marderfeld2,

Peter Krotnev2, Marc-Andre LaCroix2, David Cassan1 Huawei Technologies, Toronto, Canada Huawei Technologies, Ottawa, Canada 1 2 Recent advances in ADCs have enabled DSP-based