A 139µW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs comparator non-idealities (e.g., signal-dependent delay) degrade the SQNR mostly in the main feedback path and not the auxiliary path. No extra fast path DAC or summing network is needed.

📋 论文概要

本文提出了一种低功耗连续时间ΔΣ调制器，采用斩波交流耦合OTA堆叠和FIR DAC技术，实现了139µW功耗、104.8dB动态范围和24kHz带宽，同时有效抑制了比较器非理想性。

💡 主要创新点

• 采用斩波交流耦合OTA堆叠结构，在无尾电流源情况下实现高共模抑制比，降低功耗。
• 引入FIR DAC技术，有效缓解比较器非理想性对性能的影响。
• 设计两种OTA版本（1-stack和3-stack）进行对比验证，其中3-stack版本通过自偏置和复制网络产生参考电压，提升线性度。

🏷 关键词

📄 原文摘要

The first integrator, shown in Fig. 10.2.3, is realized by a 4-stage amplifier with feedforward compensation. Two versions of the OTA, a 1- and 3-stack, were designed for comparison. For the tailless 3-stack version, the central inverter is self-biased at VDD/2 and the intermediate devices to reference voltages generated by a replica network. Despite the lack of a tail source to degenerate the common-mode (CM) gain, high common-mode rejection (CMR) is achieved due to the self-feedback in the intermediate differential pairs [1] and the loops biasing the top- and bottom-most differential pairs, along with chopping and filtering. With fchop=900kHz and an OTA -3dB high-pass corner of ~30kHz, CM signals are significantly attenuated (e.g., >50dB at 60Hz). The notch width in the frequency response around multiples of fchop is <60kHz for the stacked-OTA, significantly less than the -3dB width of the FIR feedback nulls (>250kHz). Selection of

👥 作者与机构

Somok Mondal1,2, Omid Ghadami1, Drew A. Hall1