← 返回论文列表 📄 下载原文 PDF  ISSCC 2021 · 5.8
ISSCC 2021Session 5 · ANALOG INTERFACESAnalog Circuits

A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文提出一种5V动态Class-C并联单级放大器,通过近零死区控制和电流再分配轨到轨技术,实现了低静态电流下快速建立时间和高输出电流驱动能力,解决了传统缓冲放大器在大负载驱动时功耗与性能的权衡问题。

💡 主要创新点

重要性
发表年份
ISSCC 2021

🏷 关键词

缓冲放大器低静态电流高转换速率轨到轨动态Class-C

📄 原文摘要

One of the most key analog blocks in VLSI is probably the buffer amplifier dedicated to driving large off-chip loads. However, achieving fast settling-time and high output current drivability over a wide input voltage range has been challenging with low quiescent current (IQ) consumption. In energy-efficient amplifier designs, many technical breakthroughs have been made to enhance slew-rate (SR) [1-5] and wide unity-gain bandwidth (GBW) [4-6], thus far. However, prior efforts of [1,2], [4-6] might be impractical to use in high-voltage (& 5V) actuators and flat-panel displays due to their limited (no rail-to-rail) input range with low supply voltage. Despite obtaining good SR and GBW, the works of [1-3] allowed a considerable overshoot in transient response, which can impose sudden voltage stress on the load. Besides, complex stability compensation in a three-stage amplifier [6] inherently restrains achieving high SR. To

👥 作者与机构

Seok-Tae Koh, Ji-Hun Lee, Gyeong-Gu Kang, Hyunki Han, Hyun-Sik Kim

KAIST, Daejeon, Korea

分类:Analog Circuits · 年份:ISSCC 2021