⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一款1Tb容量、4b/cell（QLC）的144层浮栅3D NAND闪存，实现了40MB/s的编程吞吐量和13.8Gb/mm²的位密度，通过从TLC向QLC的转变显著提升了存储密度。
Kristopher H. Gaewsky2, Chang Wan Ha1, Rezaul Haque2, Owen W. Jungroth2, Steven Law1, Aliasgar S. Madraswala2, Binh Ngo2, Naveen Prabhu V2, Shantanu Rajwade1, Karthikeyan Ramamurthi2, Rohit S. Shenoy1, Jacqueline Snyder2, Cindy Sun1, Deepak Thimmegowda1, Bharat M. Pathak2, Pranav Kalavade1 Intel, Santa Clara, CA Intel, Folsom, CA 1 2 Continued improvement in the 3D NAND bit density is essential to satisfy the exponentially growing demand for data storage. The transition from 3b/cell (TLC) to 4b/cell (QLC) is a significant step towards delivering higher bit density. The increased program/erase (P/E) window, in 3D NAND technology, combined with improved program algorithms to alleviate interference from neighboring WL cells, has led to the successful deployment of two generations of QLC floating gate (FG) 3D NAND technology [1]. Further improvement in bit density, as well as the read and write performance will
Ali Khakifirooz1, Sriram Balasubrahmanyam2, Richard Fastow1,