A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration

📋 论文概要

本文提出了一种基于无复制DTC背景校准的紧凑型分数输出分频器，解决了传统DTC校准对PVT敏感的问题。该设计在0.008mm²面积和1.5mW功耗下实现了0.625至200MHz的频率范围和120fsrms的抖动性能。

💡 主要创新点

• 提出无复制DTC的背景校准技术，消除了对复制DTC的依赖，降低了面积和功耗。
• 实现了极小的芯片面积（0.008mm²）和低功耗（1.5mW），同时保持宽频率范围和低抖动。
• 通过背景校准自动补偿PVT变化，提高了输出时钟的鲁棒性。

🏷 关键词

📄 原文摘要

A compact, low-power, low-jitter clock system supporting multiple output frequencies is required in many applications. Using several PLLs to generate multiple frequencies consumes large power and chip area [1]. Alternatively, fractional output dividers (FODs) can be employed (Fig. 29.5.1, top) to generate multiple outputs [2-5]. In an FOD, the fractional division is realized by dithering a multi-modulus divider (MMD). The digitalto-time converter (DTC) is used to compensate for the quantization error due to dithering. However, the DTC characteristic is PVT sensitive and requires calibration to mitigate the variation. Prior work adopted additional replica DTCs to realize the DTC gain calibration [2]. Since DTC often dominates power and area in an FOD design, extra DTCs lead to large power and area penalties [2,3]. Furthermore, mismatch among replica and main DTCs degrades FOD performance. Figure 29.5.1 shows the proposed FOD with replica-DTC-free calibration where the DTC

👥 作者与机构

Chun-Yu Lin, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin

National Taiwan University, Taipei, Taiwan