A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS

📋 论文概要

本文提出了一种基于DAC的PAM-4发射器，采用8抽头前馈均衡（FFE），在10nm CMOS工艺中实现了224Gb/s的数据率。该设计旨在满足高性能计算、网络和AI应用对更高吞吐量的需求。

💡 主要创新点

• 采用DAC-based架构实现224Gb/s PAM-4发射，达到业界领先的数据率。
• 集成了8抽头FFE，有效地补偿信道损耗，提高信号质量。
• 在10nm先进工艺上实现，展示了高速串行链路的最新进展。

🏷 关键词

📄 原文摘要

Bong Chan Kim1, Stephen Kim1, Yutao Liu1, Savyassachi Keshava Murthy1, Priya Wali1, Kai Yu1, Hyung Seok Kim1, Chuan-chang Liu1, Dongseok Shin1, Ariel Cohen3, Yongping Fan1, Frank O’Mahony1 Intel, Hillsboro, OR Foundation Devices, Boston, MA 3 Intel, Jerusalem, Israel 1 2 *Equally-Credited Authors (ECAs) Wireline IOs have doubled per-lane data-rate every 3-4 years over the last two decades due to increasing demand in high-performance computing, networking/communications, and most recently from machine learning and AI. To address the need for higher throughput, this paper presents a 224Gb/s DAC-based PAM-4 TX with 8-tap FFE in 10nm CMOS technology. Doubling the data-rate from 112Gb/s while supporting the same PAM-4 modulation requires doubling the pad and internal net bandwidth and reducing the clocking jitter and circuit noise PSD by 2# while maintaining swing, linearity, and reliability requirements. These are addressed by combining a low-noise on-chip LC-PLL,

👥 作者与机构

Jihwan Kim*1, Sandipan Kundu*1, Ajay Balankutty1, Matthew Beach2,