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ISSCC 2021Session 11 · ADVANCED WIRELINE LINKS AND TECHNIQUESWireline I/O7nm CMOS

A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS

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📋 论文概要

该论文提出了一款工作于26.5625至106.25Gb/s的极短距离(XSR)SerDes收发器,采用7nm CMOS工艺,实现了1.55pJ/b的高能效。解决了高密度交换ASIC中对高带宽、小面积和低功耗SerDes的需求。

💡 主要创新点

核心指标
26.5625-106.25Gb/s, 1.55pJ/b
工艺节点
7nm CMOS
重要性
发表年份
ISSCC 2021

🏷 关键词

SerDesXSR高能效7nm CMOS高带宽

📄 原文摘要

George Ng1, Nanyan Wang2, Javid Musayev1, Gairik Dutta1, Masumi Shibata1, Arash Moradi1, Haleh Vahedi1, Manavi Farzad1, Prabhnoor Kainth1, Matt Yu1, Nhat Nguyen2, Jennifer Pham1, Angus McLaren1 Rambus, Toronto, Canada Rambus, San Jose, CA 1 2 The increasing connectivity of devices in our daily lives has driven the need for higher bandwidth in network and data centers. Recently, we have seen the development of 112Gb/s SerDes, particularly for long-reach interfaces [1-3]. In high-density switch ASICs, we see an increasing demand to improve both area efficiency (mm2/lane) and signaling efficiencies (pJ/b) [1-6]. In a switch ASIC, keeping the SerDes power low translates into broader system power savings since additional power and cost for cooling can be limited or even avoided entirely. One path forward to achieve these important system gains is co-packaged optics (CPO) with an extra-short-reach (XSR) interface. In

👥 作者与机构

Ravi Shivnaraine1, Marcus van Ierssel1, Kamran Farzan1, Dominic Diclemente1,

分类:Wireline I/O · 年份:ISSCC 2021