A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm

📋 论文概要

本文提出了一种基于ADC/DSP的可扩展自适应高速收发器架构，支持1.25至56Gbps/112Gbps的速率范围，采用决策导向最小均方误差（MMS）算法。该架构旨在满足超大规模数据中心、边缘计算和5G基础设施对不同速率SerDes的需求。

💡 主要创新点

• 提出可扩展的ADC/DSP架构，支持从1.25Gbps到112Gbps的宽速率范围，实现自适应速率调整。
• 采用决策导向MMS算法，优化均衡和时钟恢复，提升高速传输的鲁棒性。

🏷 关键词

📄 原文摘要

Larry Moser1, Yang Zhang1, Xiaolong Liu1, Man Pio Lam1, Haikun Jia2,3, Quan Pan2,4, Wing Hong Szeto2, Chi Fai Tang2, Ka Fai Mak2, Khawar Sarfraz2, Tairan Zhu1, Ming Kwan1, Emily Yim Lee Au1, Cormac Conroy1, Kai Keung Chan1 eTopus Technology, San Jose, CA eTopus Technology, Hong Kong, China 3 now with Tsinghua University, Beijing, China 4 now with Southern University of Science and Technology, Shenzhen, China 1 2 *Equally-Credited Authors (ECAs) The proliferation of hyperscale data centers, as well as edge and 5G infrastructure buildouts, requires SerDes running at different rates, over different insertion losses, and in different environments. This work presents a scalable ADC/DSP-based transceiver architecture that runs from 1.25Gb/s NRZ to 56Gb/s PAM-4 in 16nm, supporting channels from very short reach (VSR) at 10dB to long reach (LR) above 35dB. A followon design supports 1.25Gb/s NRZ to 112Gb/s PAM-4 in 7nm, and its measured results

👥 作者与机构

Danfeng Xu*1, Yu Kou*1, Paul Lai*,1, Zichuan Cheng1, Tze Yin Cheung2,