⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种基于eDRAM的存内计算（CIM）设计，通过可重构的嵌入式动态存储器阵列实现自适应数据转换器，旨在解决机器学习加速器中数据移动带来的内存墙瓶颈问题。该设计利用1T1C DRAM位单元进行模拟计算，结合混合信号外围电路，提高能效和计算精度。
has led to massive amounts of data movement from off-chip memory to on-chip processing cores in modern machine learning (ML) accelerators. Compute-in-memory (CIM) designs performing analog DNN computations within a memory array, along with peripheral mixed-signal circuits, are being explored to mitigate this memory-wall bottleneck: consisting of memory latency and energy overhead. Embedded-dynamic random-access memory (eDRAM) [1,2], which integrates the 1T1C (T=Transistor, C=Capacitor) DRAM bitcell monolithically along with high-performance logic transistors and interconnects, can enable custom CIM designs. It offers the densest embedded bitcell, a low pJ/bit access energy, a low soft error rate, high-endurance, high-performance, and highbandwidth: all desired attributes for ML accelerators. In addition, the intrinsic charge
Shanshan Xie1, Can Ni1, Aseem Sayal1, Pulkit Jain2, Fatih Hamzaoglu2, Jaydeep P. Kulkarni1
University of Texas, Austin, TX Intel, Hillsboro, OR 1 2 The unprecedented growth in deep neural networks (DNN) size