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ISSCC 2021Session 32 · FREQUENCY SYNTHESIZERSClocking & PLLs

A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays

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📋 论文概要

该论文提出了一种基于锁相环的本地振荡器移相系统,通过数字后台相位偏移校正技术,在12.9至15.1GHz频率范围内实现了98.4fs的抖动性能,解决了5G毫米波通信中对超低抖动和精确波束控制的需求。

💡 主要创新点

核心指标
98.4fs jitter @ 12.9-15.1GHz
重要性
发表年份
ISSCC 2021

🏷 关键词

锁相环本地振荡器移相数字后台校正

📄 原文摘要

Francesco Buccoleri1, Luca Avallone2, Angelo Parisi1, Dmytro Cherniak3, Andrea L. Lacaita1, Michael Peter Kennedy2, Carlo Samori1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy University College Dublin, Dublin, Ireland 3 Infineon Technologies, Villach, Austria 1 2 *Equally Credited Authors (ECAs) Achieving long-distance, high data-rate wireless connections at the 5G millimeter-wave (mm-wave) frequency bands requires ultra-low-jitter local oscillators (LOs) [1-3] and phased-arrays with very accurate beam-steering capability [4,5]. In regard to jitter, digital bang-bang phase-locked loops (BBPLLs) have been recently shown as capable of satisfying the very stringent requirements, while at the same time occupying less area than their analog counterparts [3]. This makes them particularly well-suited to the socalled localized LO-generation approach, where a synthesizer is placed in each of the

👥 作者与机构

Alessio Santiccioli*1, Mario Mercandelli*1, Simone M. Dartizio*1,

Francesco Tesolin1, Saleh Karman1, Abanob Shehata1, Luca Bertulessi1,

分类:Clocking & PLLs · 年份:ISSCC 2021