Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing

📋 论文概要

本文提出了一种峰值电流控制的集成高频降压稳压器，采用22nm CMOS工艺，通过多片并联（ganged）架构实现高电流密度和高效率，解决了高性能多核处理器和GPU在单电压/功率域下的大电流供电问题。

💡 主要创新点

• 提出峰值电流控制方法，实现多片并联稳压器的均流和快速瞬态响应。
• 采用22nm CMOS工艺和封装内空气芯电感，实现高频率、高电流密度的全集成电压调节器。
• 通过多片并联架构支持大电流输出，同时保持紧凑面积和低分布损耗。

🏷 关键词

📄 原文摘要

Suhwan Kim1, Xiaosen Liu1, Huong T. Do2, Kaladhar Radhakrishnan2, Krishnan Ravichandran1, James W. Tschanz1, Vivek De1 Intel, Hillsboro, OR Intel, Chandler, AZ 1 2 High-performance many-core processors and GPUs demand 100s of Watts of power in a single voltage/power domain on chip, operating below 1V. High-frequency and highcurrent-density fully integrated voltage regulators (FIVRs) with in-package air core inductors (ACIs) [1] or on-package magnetic inductors can deliver power with high efficiency and low distribution losses in compact footprints. Multiple FIVR tiles must be “ganged” to support the large on-chip voltage/power domains while meeting the reliability constraints of the active and passive elements, and maintaining high overall efficiency. Ganging multiple tiles of traditional IVRs with voltage-mode control (VMC) can result in different currents being drawn from each IVR tile due to mismatches in the inductors,

👥 作者与机构

Nachiket Desai1, Harish K. Krishnamurthy1, Khondker Ahmed1, Sheldon Weng1,