A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7µW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

📋 论文概要

本文提出了一款用于物联网终端节点的全集成10核SoC，采用MRAM实现状态保持，并具有1.7µW的超低功耗认知唤醒功能，解决了IoT设备对高能效和低待机功耗的需求。该SoC在32GOPS下达到1.3TOPS/W的能效，并集成了专用ML加速器以进一步提升性能。

💡 主要创新点

• 集成了10个RISC-V核心的SoC，在32GOPS下实现1.3TOPS/W的高能效，并支持614GOPS/W的峰值能效。
• 采用MRAM实现非易失性状态保持，并设计了1.7µW的认知唤醒电路，大幅降低待机功耗。

📄 原文摘要

Alfio Di Mauro2, Marco Guermandi1,3, Giuseppe Tagliavini1, Antonio Pullini2,3, Igor Loi3, Jie Chen1,3, Eric Flamand2,3, Luca Benini1,2 University of Bologna, Bologna, Italy ETH Zurich, Zurich, Switzerland 3 Greenwaves Technologies, Grenoble, France 1 614GOPS/W, and up to 3.3GFLOPS and 129GFLOPS/W, on GP processors, demonstrating leading-edge performance on a wide range of NSAA (Fig. 4.4.3). Efficiency can be further increased by exploiting a dedicated ML accelerator (HW computing element: HWCE) sharing L1 memory with the RISC-V cluster through four additional ports for streamlined zero-copy HW-SW cooperation. The HWCE has three multi-precision (4b/8b/16b) 3×3 convolution units with 27 MACs in total, as well as integrated normalization / activation, leading to 32.2GOPS and 1.3TOPS/W. Fig. 4.4.4 shows performance and efficiency of multi-precision matrix multiplication running on General-Purpose (GP) processors and 8b DNN workloads running on the SoC and on

👥 作者与机构

Davide Rossi1, Francesco Conti1, Manuel Eggiman2, Stefan Mach2,