A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

📋 论文概要

提出一种支持集合关联块级零跳过和乒乓计算内存储（CI）技术的神经网络处理器，能效范围为2.75至75.9 TOPS/W。解决了传统CIM芯片在稀疏性支持和系统级设计方面的挑战，实现了高能效的边缘端推理。

💡 主要创新点

• 引入集合关联块级零跳过机制，有效利用权重和激活的稀疏性减少计算功耗。
• 采用乒乓CI（计算内存储）架构，通过流水线操作提高处理单元利用率。

🏷 关键词

📄 原文摘要

Zhe Yuan1, Mingtao Zhan1, Jiaxin Liu1, Jian-Wei Su3, Yen-Lin Chung3, Ping-Chun Wu3, Li-Yang Hung3, Meng-Fan Chang3, Nan Sun1, Xueqing Li1, Huazhong Yang1, Yongpan Liu1 Tsinghua University, Beijing, China Pi2star Technology, Beijing, China 3 National Tsing Hua University, Hsinchu, Taiwan 1 2 Computing-in-memory (CIM) is an attractive approach for energy-efficient neural network (NN) processors, especially for low-power edge devices. Previous CIM chips [1-5] have demonstrated macro and system-level design enabling multi-bit operations and sparsity support. However, several challenges exist, as shown in Fig. 15.2.1. First, though a previously proposed block-wise sparsity strategy [5] can power off ADCs, zeros still contributed to storage requirements, and power gating was not applied to computing resources. Second, on-chip SRAM CIM macros are not large enough to hold all weights. Updating weights between computing operations leads to significant performance loss.

👥 作者与机构

Jinshan Yue1,2, Xiaoyu Feng1, Yifan He1, Yuxuan Huang1, Yipeng Wang2,