A 144Kb Annealing System Composed of 9×16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems

📋 论文概要

本文提出一个由9个16Kb退火处理器芯片组成的144Kb退火系统，通过可扩展的片间连接实现大规模组合优化问题的求解，解决了单芯片退火处理器规模受限的问题。

💡 主要创新点

• 利用多芯片级联技术将退火处理器扩展到更大规模，实现144Kb系统。
• 设计可扩展的片间连接方式，支持芯片间高效通信与协同退火。

🏷 关键词

📄 原文摘要

Service, Sapporo, Japan 1 2 Substantial progress has been made on a new computer architecture, known as an annealing processor (AP) [1–4]. The AP can effectively solve NP-hard combinatorial optimization problems by providing a fast method for finding the grand state of an Ising model. In particular, various types of APs based on a CMOS process (CMOS-AP) significantly improve the scalability and power efficiency of the annealing system by utilizing fast parallel spin updates on the basis of simulated annealing (SA) [2-4]. Further development of CMOS-APs requires overcoming two challenges: improving the accuracy of the annealing processing by expanding the bitwidth of coefficients and attaining a multi-chip annealing system consisting of AP chips with 8-way connectivity. In this work,

👥 作者与机构

Takashi Takemoto1, Kasho Yamamoto2, Chihiro Yoshimura2, Masato Hayashi2,

Masafumi Tada3, Hiroaki Saito4, Mayumi Mashimo2, Masanao Yamaoka2 Hitachi, Sapporo, Japan Hitachi, Tokyo, Japan 3 Toppan Technical Design Center, Sapporo, Japan 4 Total Design