A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a

📋 论文概要

本文提出了一款16Gb容量、工作电压低于1V、数据速率达7.14Gb/s/pin的LPDDR5 SDRAM。通过采用Mosaic架构、短反馈1-tap判决反馈均衡器（DFE）、FSS总线以及低电平体偏置技术，在第三代10nm DRAM工艺上实现了高性能与低功耗。

💡 主要创新点

• 提出Mosaic架构，优化了DRAM内部数据路径和布局，提升带宽和能效。
• 采用短反馈1-tap DFE，有效补偿高速信号传输中的信道损耗，提高数据眼图裕度。
• 引入FSS总线与低电平体偏置技术，降低功耗并改善信号完整性。

🏷 关键词

📄 原文摘要

Body Biasing in a 3rd-Generation 10nm DRAM Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae-Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chan-Young Kim, Byong-Wook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee Samsung Electronics, Hwaseong, Korea The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA.

👥 作者与机构

Mosaic Architecture with a Short-Feedback 1-Tap DFE, an, FSS Bus with Low-Level Swing and an Adaptively Controlled