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提出一种4阶连续时间Delta-Sigma调制器，仅使用一个运算跨导放大器（OTA）和2阶噪声整形逐次逼近寄存器（NS-SAR）量化器，实现了3.7mW功耗、12.5MHz带宽和81dB SNDR。解决了传统多OTA CTDSM设计复杂、功耗高和稳定性差的问题。
design suffers from a few challenges. First, it requires a large number of OTAs [1]. This increases the design complexity and power. In addition, each OTA contributes extra phase delay, whose reduction requires increasing the OTA BW, further increasing power. Second, it is harder to stabilize, especially considering PVT variations. For example, a slight change in the RC time constant can cause instability. One way to address these issues is to use a passive discrete-time (DT) noise-shaping (NS) SAR ADC as quantizer [2], [3]. In [2], a 3rd-order DSM is built with only 1 OTA and a 2nd-order NS-SAR. Since it is set by device ratios, the NTF of a NS-SAR is PVT-robust. Hence, the 3rd-order DSM stability is equivalent to that of a 1st-order CTDSM, which is easy to ensure. Nevertheless, because
Wei Shi1, Jiaxin Liu2, Abhishek Mukherjee1, Xiangxing Yang1, Xiyuan Tang1,
Linxiao Shen1, Wenda Zhao1, Nan Sun1,2 University of Texas, Austin, TX Tsinghua University, Beijing, China 1 2 A high-order CTDSM can provide high resolution with a small OSR, but its