A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS

📋 论文概要

该论文提出了一种分布式数字低压差稳压器（DLDO），通过时分复用校准环路实现高电流密度和宽负载范围，解决了高性能计算和AI应用中微处理器热功率预算限制下的高效供电问题。

💡 主要创新点

• 采用时分复用校准环路，在多个LDO单元间共享校准资源，降低功耗和面积开销。
• 实现40A/mm²的高电流密度和1mA至6.4A的宽负载范围，显著提升供电效率。

🏷 关键词

📄 原文摘要

microprocessors for applications such as HPC and AI, the available power is strictly limited by the thermal power budget. To overcome this limitation, recently, each core has been implemented with a dedicated integrated voltage regulator to increase the efficiency of power usage. Distributed digital LDO (DLDO) is a powerful solution for the integrated voltage regulator because it can supply uniform power over the entire core with reduced IR drop and help the thermal management [1-4]. In the previous distributed DLDOs [1-3], even though all LDO outputs are connected to drive the power-delivery network, the LDOs operate independently using their own controller, which occupies a large portion of the LDO size. Therefore, the current density in these types of structures is low. In [4], the

👥 作者与机构

Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, SangHo Kim,

Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin Samsung Electronics, Hwaseong, Korea Although the number of cores is increasing continuously in modern