A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters

📋 论文概要

该论文提出了一种64GS/s 4倍插值1位半数字FIR DAC，用于射频采样ADC的宽带校准和内置自测试。它解决了在先进数字CMOS工艺中集成复杂DSP与射频前端以实现软件定义基站无线电时，对高效紧凑数据转换器的需求。

💡 主要创新点

• 采用4倍插值和1位半数字FIR DAC架构，实现了64GS/s的高速转换速率。
• 将DAC设计用于宽带校准和内置自测试（BIST），提升了射频采样ADC系统的自校准能力。

🏷 关键词

📄 原文摘要

Yu-shan Wang4, Christian Lindholm2, Hundo Shin5, Ramon Sanchez3, Christoph Duller2, Patrick Torta2, Kamran Azadet1 Intel, Santa Clara, CA Intel, Villach, Austria 3 Intel, Madrid, Spain 4 Intel, Hillsboro, OR 5 now with Apple, Cupertino, CA 1 2 *Equally-Credited Authors (ECAs) The integration of complex DSP functions together with the entire RF-frontend enables software-defined base-station radio and mandates the availability of power-efficient and compact data converters in advanced digital CMOS processes. In a self-calibrated RFsampling ADC-system, a co-integrated digital non-linear post-equalizer (NLEQ) can substantially increase the receiver performance [1], but wideband ADC-calibration also requires a wideband, calibration-free and ultra-linear reference signal source to train the NLEQ-coefficients during a dedicated calibration period, for example at startup, or during maintenance intervals. Another function with renewed importance in complex transceiver

👥 作者与机构

Martin Clara*1, Daniel Gruber*2, Albert Molina3, Matteo Camponeschi2,