An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

📋 论文概要

该论文提出了一款基于SRAM的全数字存内计算宏，在22nm工艺下实现全精度运算，适用于机器学习推理。它解决了传统存内计算中模拟/混合信号设计复杂度高、精度损失的问题，达到了89TOPS/W的能效和16.3TOPS/mm2的面积效率。

💡 主要创新点

• 首次实现全数字、全精度的SRAM存内计算，避免了模拟域的非理想性和精度损失。
• 通过创新的电路架构和设计优化，在22nm工艺下同时实现了极高的能效和面积效率。

🏷 关键词

📄 原文摘要

Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang TSMC, Hsinchu, Taiwan From the cloud to edge devices, artificial intelligence (AI) and machine learning (ML) are widely used in many cognitive tasks, such as image classification and speech recognition. In recent years, research on hardware accelerators for AI edge devices has received more attention, mainly due to the advantages of AI at the edge: including privacy, low latency, and more reliable and effective use of network bandwidth. However, traditional computing architectures (such as CPUs, GPUs, FPGAs, and even existing AI accelerator ASICs) cannot meet the future needs of energy-constrained AI edge applications. This is because ML computing is data-centric, most of the energy in these

👥 作者与机构

Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee,