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ISSCC 2021Session 35 · ADAPTIVE DIGITAL TECHNIQUES FOR VARIATION TOLERANT SYSTEMSDigital Circuits7nm FinFET

An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文实现了一款采用7nm FinFET工艺的异构八核CPU,用于5G智能手机SoC。通过片上传感器(过程、电压、温度、老化)动态调整guardband,优化动态频率和电压缩放(DVFS),实现了高速度和低功耗。

💡 主要创新点

工艺节点
7nm FinFET
重要性
发表年份
ISSCC 2021

🏷 关键词

八核CPU传感器辅助动态频率电压缩放7nm FinFET智能手机SoC

📄 原文摘要

Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, YS Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang MediaTek, Hsinchu, Taiwan A high-speed and power-efficient heterogeneous octa-core CPU complex is realized in a 7nm FinFET process. On-chip sensors that handle guard band in terms of process (VPGB), voltage, temperature (VTGB), and aging (VAGB) are designed for power enhancement in dynamic frequency and voltage scaling (DVFS). A process sensor (Psensor) is used to determine per-die VPGB for Smartphone operation voltage (Vsov) with machine learning (ML). A temperature sensor (T-sensor) senses run-time local thermal and temperature inversion (T-inversion) to scale VTGB in DVFS. An aging sensor (Asensor) converts cell degradation to corresponding VAGB for aging compensation. Lastly, a voltage sensor (V-sensor) sustains system stability against supply noise. With sensor

👥 作者与机构

Bo-Jr Huang, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Rory Huang, Angus Lin,

分类:Digital Circuits · 年份:ISSCC 2021