A 12b 600MS/s Pipelined SAR and 2×-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET chip-to chip gain variation of the residue signal path. Moreover, the area-consuming 7b CDAC can be used in calibrating inter-stage offset error by adding offset in the feedback signal. Therefore, the comparator without offset calibration enables the SAR to enhance conversion speed.

📋 论文概要

提出一种12位600MS/s的流水线SAR与2倍交织增量Delta-Sigma混合架构ADC，采用源跟随器实现残差传输，解决了高速高精度转换中的时序与噪声问题。通过自适应速度控制时钟生成方案，结合同步与异步优点，利用背景频率校准产生固定占空比和持续时间的内时钟，确保DAC建立时间，提升了PVT鲁棒性。

💡 主要创新点

• 提出自适应速度控制时钟生成方案，通过背景频率校准产生固定50%占空比和固定持续周期的内部操作时钟，兼顾同步与异步模式的优点，提高PVT稳定性。
• 采用源跟随器实现残差电压的高线性传输，降低功耗并简化残差放大器设计，适用于流水线SAR与增量Delta-Sigma的混合架构。
• 将2倍交织增量Delta-Sigma ADC与流水线SAR结合，通过交织增强速度，利用增量Delta-Sigma提高分辨率，实现12位600MS/s性能。

🏷 关键词

📄 原文摘要

Youngjae Cho, Jongshin Shin Figure 10.5.3 shows the proposed adaptive speed-controlled (ASC) clock generation scheme. The ASC clock generator takes advantages from both the synchronous and asynchronous schemes by generating a 50% duty and duration-fixed internal operation clock (CKASC) cycles, regardless of the PVT variations, by background frequency calibration. The ASC clock generator dedicates at least a 1/2 clock period of CKASC for the internal DAC settling time. In fact, the DAC settling initiates as soon as the comparator makes the decision (just like the asynchronous operation) that dedicates more than ½ the clock period of CKASC for additional performance enhancement. At the end of the data conversion, a shift-register in the SAR logic counts the number of CKASC cycles and generates the end-of-conversion (EOC) signals. As shown in Fig. 10.5.3, the ASC clock generator calibrates the frequency of CKASC in the background by reducing or

👥 作者与机构

Seungyeob Baek, Ilhoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim,