80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with SelfReferenced Asynchronous Adaptive Droop Mitigation

📋 论文概要

该论文提出一种在10nm CMOS工艺下实现的0.4至6.5GHz频率锁定环（FLL）时钟发生器，支持80ns快速锁定和自适应频率合成，用于高性能SoC的DVFS场景，解决了计算引起的供电电压下垂导致的保护带问题。

💡 主要创新点

• 提出自参考异步自适应下垂缓解技术，能在0.5-1.0ns内响应供电电压下垂，减少保护带浪费。
• 采用快速锁定FLL架构，实现80ns内完成任意频率切换且出口频率误差小于1%，支持650MHz/100ns的渐变频率转换。

🏷 关键词

📄 原文摘要

4-to-6.5GHz Frequency Locked Loop (FLL) implemented in 10nm CMOS, targeting high performance SoCs that require uninterrupted, overshoot-free clocks for Dynamic Voltage and Frequency Scaling (DVFS). The FLL supports gradual frequency transitions (e.g. up to 650MHz per 100ns) where di/dt constraints prevail. When unconstrained, transitions between any two frequencies in 100ns with <1% exit frequency error are possible. Adaptive Frequency Synthesis (AFS), with 0.5-to-1.0ns reaction time, helps mitigate guardbands induced by computation-dependent supply droop [1-3]. Split analog and digital supplies (each driven by a low drop out regulator (LDO), see Fig. 29.3.1) and duty cycle adjustment (DCA) improve output jitter performance and clock quality. The Digitally Controlled Oscillator (DCO) at the FLL’s heart is based on the 5-stage ring

👥 作者与机构

Praveen Mosalikanti, Qi Wang, Kuan-Yueh James Shen, Mark Neidengard,

Syed Feruz Syed Farooq, Vaughn Grossnickle, Nasser Kurd Intel, Portland, OR We present a 0