A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips VGBL= (VMM15 × CGBL15 + VMM14 × CGBL14 + … + VMM0 × CGBL0)/(CGBL15 + CGBL14 + … + CGBL0). The voltage of GBLB (VGBLB) is the pMACV of 2bIN×1bW with 16-channel accumulation using the LSB part of a 4b-input (IN10).

📋 论文概要

该论文提出了一款基于28nm工艺的384kb 6T-SRAM计算存储一体化宏单元，支持8位精度，用于AI边缘芯片。通过采用一种结合3位SAR和2位单斜坡ADC的Ph-ADC结构以及顺序低MACV优先方案，在实现高精度乘累加向量读取的同时降低了功耗和面积开销。

💡 主要创新点

• 提出了一种新型Ph-ADC结构，融合3位SAR ADC和2位单斜坡ADC，实现高精度MACV读取并控制面积和功耗。
• 采用了顺序低MACV优先方案，优先处理较小的MACV值，从而减少ADC转换次数和整体能耗。
• 在28nm工艺下实现了384kb容量的6T-SRAM CIM宏单元，支持8b精度，适用于AI边缘芯片的能效需求。

🏷 关键词

📄 原文摘要

Ping-Chun Wu1, Yen-Lin Chung1, Li-Yang Hung1, Jin-Sheng Ren1, Tianlong Pan1, Sih-Han Li2, Shih-Chieh Chang2, Shyh-Shyuan Sheu2, Wei-Chung Lo2, Chih-I Wu2, Xin Si1, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Meng-Fan Chang1,3 Figure 16.3.4 shows the proposed Ph-ADC’s operation: comprising of a 3b SAR ADC and a 2b single-slope (SS) ADC, with a sequential low-MACV-first scheme and a custom reference voltage generator. SAR ADCs are commonly used in CIMs for high-precision MACV readout operations, at the expense of a high area overhead and large power consumption due to their large capacitance (32C for 5b conversion). On the other hand, SS-ADCs require less area, but impose long latency: 31 sensing phases for a 5b conversion. To reduce power consumption, area overhead, and latency, the Ph-ADC uses an SS-ADC to convert the 2 least significant bits (LSBs), and a SAR-ADC to convert

👥 作者与机构

Jian-Wei Su*1,2, Yen-Chi Chou*1, Ruhui Liu1, Ta-Wei Liu1, Pei-Jung Lu1,