A 56Gb/s 50mW NRZ Receiver in 28nm CMOS

📋 论文概要

该论文提出了一款采用28nm CMOS工艺的56Gb/s NRZ接收器，通过模拟域设计实现了仅50mW的功耗，相比传统方案功耗降低超过两倍。该接收器在信道损耗较大的情况下仍能保持低于10^-12的误码率，解决了高速率下功耗与性能的平衡问题。

💡 主要创新点

• 采用全模拟域NRZ接收器架构，避免了ADC的高功耗开销，实现功耗降低超过两倍。
• 针对高损耗信道优化了接收器电路设计，在56Gb/s速率下达到BER<10^-12的同时仅消耗50mW。
• 在28nm CMOS工艺上实现了50mW超低功耗，为高速有线通信提供了低功耗解决方案。

🏷 关键词

📄 原文摘要

The power consumption of wireline transceivers has become increasingly critical as higher data rates and a larger numbers of lanes per chip are sought [1-6]. While attractive for lossy channels, PAM-4 signaling has mostly dictated ADC-based receivers (RXs) and relatively high power consumption [1,2]. Non-return-to-zero (NRZ) receivers, on the other hand, can be realized in the analog domain, potentially consuming less power, but they must deal with a greater loss. This paper introduces an NRZ RX that achieves more than a twofold reduction in power while exhibiting BER < 10-12 for a channel loss of 25dB at 28GHz. The proposed design can compete with PAM-4 counterparts and/or serve in 112Gb/s systems that must also support 56Gb/s reception. Figure 11.7.1 shows the RX architecture. The data path consists of a CTLE core, a DFE core, a discrete-time linear equalizer (DTLE) [4], and a DMUX. The receiver performance

👥 作者与机构

Atharav Atharav, Behzad Razavi

University of California, Los Angeles, CA