A 65nm 3T Dynamic Analog RAM-Based Computing-inMemory Macro and CNN Accelerator with Retention

📋 论文概要

本文提出了一种基于65nm 3T动态模拟RAM的内存计算宏与CNN加速器，通过保持增强和自适应模拟稀疏性技术，实现了44TOPS/W的系统能效，解决了高精度模拟内存计算中的稀疏性和保留问题。

💡 主要创新点

• 采用3T动态模拟RAM单元实现内存计算，支持模拟域的高效运算。
• 引入保持增强技术，改善模拟存储单元的电荷保持特性。
• 提出自适应模拟稀疏性方法，动态利用输入稀疏性以降低功耗。

🏷 关键词

📄 原文摘要

computing inside memory macros have shown significant advantages in computing efficiency for deep learning applications. While earlier CIM macros were limited by lower bit precision, e.g. binary weights in [1], recent works have shown 4-to-8b precision for the weights/inputs and up to 20b for the output values [2, 3]. Sparsity and application features have also been exploited at the system level to further improve the computation efficiency [4, 5]. To enable higher precision, bit-wise operations were commonly utilized [3, 4]. However, there are limitations in existing solutions using the bit-wise operations with SRAM cells. Fig. 15.3.1 shows the summary of challenges and solutions in this work. First, all existing solutions utilize 6T/8T/10T SRAM as a CIM cell, which fundamentally limits the size of

👥 作者与机构

Enhancement, Adaptive Analog Sparsity and 44TOPS/W, System Energy Efficiency

Zhengyu Chen, Xi Chen, Jie Gu Northwestern University, Evanston, IL Computing-In-Memory (CIM) techniques which incorporate analog