A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection

📋 论文概要

本文提出了一款可编程卷积成像SoC，采用电流域三元加权MAC操作，在传感器内实现卷积计算，解决了像素级处理限制感受野的问题，能效范围为0.2-3.6 TOPS/W。

💡 主要创新点

• 提出电流域三元加权MAC操作，在传感器内实现高效卷积计算，避免像素级处理单元对像素间距和感受野的限制。
• 实现可编程卷积成像SoC，支持多尺度操作，适用于低功耗嵌入式计算机视觉应用。
• 能效范围0.2-3.6 TOPS/W，兼顾性能与功耗。

🏷 关键词

📄 原文摘要

Mixed-signal vision chips are becoming increasingly popular for low-power embedded computer vision applications on smartphones, wearables and IoT nodes, as they meet stringent power and area constraints while maintaining a sufficient level of accuracy for low- to medium-level image processing tasks. On the one hand, in-sensor processing [1,2] enables massively parallel operation but relies on pixel-level processing elements that degrade the pixel pitch and restrict the convolutional receptive field to neighboring pixels [1], precluding multi-scale operation. On the other hand, near-sensor processing [3-5] can operate at multiple scales by pixel downsampling [3] or binning [4] but entails significant power and area overhead as an analog memory is required to store pixel values awaiting processing. In addition, previous near-sensor processing SoCs are generally application-specific and thus suffer from limited versatility. In this paper, we

👥 作者与机构

Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol

Université catholique de Louvain, Louvain-la-Neuve, Belgium