A 104fsrms-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique

📋 论文概要

该论文提出了一种15GHz分数N子采样锁相环(SSPLL)，采用电压域量化误差消除技术解决了子采样锁相环因高增益采样导致的分数分辨率难题，实现了104fsrms的抖动和-61dBc的分数杂散。

💡 主要创新点

• 提出电压域量化误差消除技术，使得子采样锁相环能够实现分数N操作而不牺牲线性范围。
• 通过创新的电路设计，在15GHz载波频率下同时实现了超低抖动和低分数杂散。

🏷 关键词

📄 原文摘要

2 *Equally Credited Authors (ECAs) Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, KSH. However, this highgain operation of a sample-and-hold circuit (SH) also has a downside that makes it difficult to achieve a fractional resolution. This is because the quantization error (Qerror) due to the non-integer relationship between the reference frequency, fREF, and the VCO frequency, fVCO, easily makes sampling points fall outside the linear range of the SH. Thus, to have a fractional resolution, SSPLLs must have a dedicated method for cancelling the Q-error. The top left of Fig. 32.4.1 shows a time-domain Q-error

👥 作者与机构

Juyeop Kim*1, Yongwoo Jo*1, Younghyun Lim*2, Taeho Seong2, Hangi Park1,

Seyeon Yoo1, Yongsun Lee3, Seojin Choi1, Jaehyouk Choi1 KAIST, Daejeon, Korea Ulsan National Institute of Science and Technology, Ulsan, Korea 3 Samsung Electronics, Hwaseong, Korea