A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <−81dBm LO Leakage Supporting Intra- and Inter-Band Carrier Aggregation

📋 论文概要

本文提出一种0.9V双通道滤波混叠接收前端，通过电阻DAC实现周期性时变电阻，结合无源混频器和积分转储电路，解决了传统N-path滤波器高LO泄漏和不支持多载波的问题。实现了+35dBm IIP3和低于-81dBm的LO泄漏。

💡 主要创新点

• 采用双通道滤波混叠架构，支持多载波操作，克服了传统N-path滤波器在多载波场景下的局限性。
• 利用电阻DAC实现周期性时变电阻，结合无源混频器和积分转储电路，在低电压下实现高线性度和低LO泄漏。

🏷 关键词

📄 原文摘要

Programmable receivers have drawn a lot of attention in recent years, especially those exploiting periodically time-varying (PTV) circuits. N-path filters and mixer-first receivers [1$3] achieve sharp filtering and good linearity but can suffer from high LO leakage (>$70dBm), which is not compliant with the FCC requirements [4]. In addition, they do not support multi-carrier operation very well [5]. The filtering-by-aliasing (FA) receiver front-end in [6] uses a resistor DAC to realize a PTV resistor, R(t), followed by a passive mixer and an integrate-and-dump circuit to achieve sharp analog FIR filtering and moderate linearity (Fig. 6.3.1). However, the PTV resistor presents a time-varying impedance at the RF node, VRF. While low S11 can be achieved in an average sense [6], it is difficult to guarantee desired filter response in the presence of complex source impedances, e.g., from parasitics. More importantly, if

👥 作者与机构

Shi Bu, Sudhakar Pamarti

University of California, Los Angeles, CA