A 14nm Analog Sampling Fractional-N PLL with a Digital-toTime Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels

📋 论文概要

该论文提出了一种采用模拟采样技术的14nm分数-N锁相环，通过数字-时间转换器范围缩减技术，实现了80fs的积分抖动，解决了DTC需要同时实现高分辨率和宽延迟范围的挑战。

💡 主要创新点

• 提出数字-时间转换器范围缩减技术，降低DTC设计难度。
• 采用模拟采样鉴相器，实现低抖动分数-N合成。

🏷 关键词

📄 原文摘要

requires sub-100fs rms jitter to support 64-QAM and 2×2 MIMO under non-ideal channel conditions [1]. Although fractional-N phaselocked loops (PLLs) employing digital-to-time converters (DTCs) and sampling phase detectors (SPDs) have demonstrated integrated jitter below 100fs [1,2], such a DTC remains the most challenging block in this PLL architecture. It needs to achieve a fine resolution (e.g., 0.3ps) for low quantization noise (QN) and a large delay range to cancel the quantization error (QE) due to the delta-sigma modulator (DSM) used for fractionalN synthesis (e.g., 400ps for a 5GHz VCO and mash1-1 DSM). The DTC also contributes to the in-band phase noise (PN) and its nonlinearity increases the fractional spur and

👥 作者与机构

Wanghua Wu1, Chih-Wei Yao1, Chengkai Guo1, Pei-Yuan Chiang1,

Pak-Kim Lau1, Lei Chen1, Sang Won Son1, Thomas Byunghak Cho2 Samsung Semiconductor, San Jose, CA 2 Samsung Electronics, Hwaseong, Korea 1 A local oscillator (LO) for 5G new radio