⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一款基于DSP的116Gb/s有线收发器，采用7nm CMOS工艺，在PAM-4/Duo-PAM-4调制下可补偿45dB插入损耗，PAM-2下补偿52dB，能效达6pJ/b。解决了高速率下高损耗信道的信号恢复和功耗效率问题。
Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto Huawei Technologies, Ottawa, Canada DSP-based transceivers above 100Gb/s have demonstrated the ability to handle up to 38dB insertion loss (IL) with low-to-moderate crosstalk [1-2]. At same time, power scaling techniques [3] have closed the energy efficiency gap compared with analog/mixed-signal transceivers on shorter links. Notwithstanding advances in materials and connectors, in large repeater-less backplanes, transceivers are required to operate reliably at 100Gb/s with more than 40dB IL. Furthermore, next generation computing and AI applications require 50Gb/s rates per lane on channels with more than 45dB loss but without the latency of forward error correction (FEC). In this paper we demonstrate
Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir,