A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur

📋 论文概要

本文提出了一种分数-N数字MDLL，采用背景两点DTC校准技术，解决了参考时钟与环形振荡器相位不对齐的问题，实现了-60dBc的分数杂散。

💡 主要创新点

• 提出背景两点DTC校准技术，无需额外参考时钟即可自动校正DTC的非线性。
• 采用分数-N数字MDLL架构，结合注入锁定和数字控制，实现了低抖动和低杂散输出。

🏷 关键词

📄 原文摘要

Inphi, Santa Clara, CA 1 2 Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scalingfriendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has been increasing interest in injecting a low-noise reference clock signal to the RO to refresh the accumulated jitter, as seen in multiplying delay-locked loops (MDLLs) and injection-locked phase-locked loops (IL-PLLs). The main challenge of this architecture is that the injection signal derived from the reference clock is not perfectly aligned with the RO phase at the injection node, hence spurious tones are generated, and this phase alignment issue is especially exacerbated in fractional-N operation as the injection time point must gradually drift away from the reference clock phase [1]. One way of achieving this required phase drift is by tuning digital-to-time converters (DTCs) according to a fractional frequency multiplication ratio; however, DTC

👥 作者与机构

Qiaochu Zhang1, Shiyu Su1, Cheng-Ru Ho2, Mike Shuo-Wei Chen1

University of Southern California, Los Angeles, CA