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ISSCC 2021Session 27 · DISCRETE-TIME ADCsData Converters

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier

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📋 论文概要

本文提出了一种0.4-40MS/s、75.7dB SNDR的全动态事件驱动流水线ADC,采用3级级联浮空逆变器放大器取代传统静态OTA,解决了传统流水线ADC功耗随采样率缩放性差以及OTA唤醒耗时长的问题,实现了宽范围可扩展的高效高精度转换。

💡 主要创新点

核心指标
0.4-40MS/s, 75.7dB SNDR
重要性
发表年份
ISSCC 2021

🏷 关键词

全动态ADC事件驱动流水线ADC浮空逆变器放大器可扩展采样率

📄 原文摘要

Tsinghua University, Beijing, China 1 2 Many applications, such as multi-standard wireless and event-driven IoT devices, demand high-resolution ADCs with scalable sampling rate and power consumption. The conventional pipelined ADC can achieve high resolution, but its power does not scale well with the sampling rate due to the use of a closed-loop static OTA for residue amplification. While the OTA can be turned off to save power, it requires considerable time for the bias circuit and CMFB loop to settle when waking up, leading to wasted power and reduced peak operation frequency. Using an open-loop dynamic amplifier can make power scale linearly with frequency, but its gain varies with PVT and often requires background calibration, which converges slowly and is incompatible with eventdriven applications. The ring-amp is a promising solution as it features closed-loop operation, easy duty-cycling, and decaying power over time [1]–[4]. However, its stability

👥 作者与机构

Xiyuan Tang1, Xiangxing Yang1, Jiaxin Liu2, Wei Shi1, David Z. Pan1, Nan Sun1,2

University of Texas, Austin, TX

分类:Data Converters · 年份:ISSCC 2021