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ISSCC 2021Session 32 · FREQUENCY SYNTHESIZERSClocking & PLLs

A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/µs Slope

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📋 论文概要

本文提出了一种基于ADPLL的24GHz自校准FMCW合成器,解决了宽频带多bank DCO的1/√LC非线性和频带重叠导致的频率不连续问题,实现了3.2GHz chirp带宽下0.01% rms频率误差。

💡 主要创新点

核心指标
0.01% rms frequency error @ 3.2GHz chirp bandwidth
重要性
发表年份
ISSCC 2021

🏷 关键词

FMCW雷达ADPLL自校准频率合成器毫米波

📄 原文摘要

for millimeter-wave (mm-wave) frequency-modulated continuous-wave (FMCW) radars. Large-chirp-bandwidth (BWchirp) sawtooth waveforms are required to be synthesized with fast slope and high-frequency linearity for accurate detection of targets or high-quality imaging. Fractional-N phase-locked loops (PLLs) with a two-point-modulation (TPM) scheme are widely used to synthesize fast highlinearity chirps [1-3]. However, for a wideband multi-bank digitally controlled oscillator (DCO), the intrinsic 1/√𝐿C nonlinearity and the frequency discontinuity from overlaps between adjacent tuning bands introduce a significant gain mismatch between the two modulation paths of the TPM scheme and degrade the chirp linearity [3,5]. To linearize the DCO tuning curve, a piecewise linear pre-distortion method is commonly used as

👥 作者与机构

Zhengkun Shen1, Haoyun Jiang1, Fan Yang1, Yixiao Wang2, Zherui Zhang1,

Junhua Liu1, Huailin Liao1 Peking University, Beijing, China University of British Columbia, Vancouver, Canada 1 2 Frequency synthesizers are critical

分类:Clocking & PLLs · 年份:ISSCC 2021